Control Flow Group Sn3S n4 10 typical Execution Sequence 1

1
Control Flow Group S(n-3)S (n-4) 10
(typical Execution Sequence) - 1

• Step 3.c.1 If Un-Conditional Transfer of
  control
• S(n-5) S(n-6) S(n-7)
  000
• THEN go to Step 3.c.2
• ELSE Conditional Transfer of
  Control
• If Condition is set
  THEN go to Step 3.c.2
• ELSE Condition
  is NOT set go to Step 3.c.7
• Step 3.c.2. Check which type of Op Code among
  the following three
• Purely Combinational
  Operation already accomplished
• during instruction decoding
  stage
• a) JUMP go to Step 3.c.5 b) CALL go to
  Step 3.c.4
• c) Software Interrupt go to Step 3.c.3.
  

2
Control Flow Group S(n-3)S (n-4) 10
(typical Execution Sequence) - 2

• Step 3.c.3 Preserve Result Flags (PSW) in
  System stack .
• Preserve Relevant Segment
  Register also in System Stack.
• For Software Interrupt
  Instruction to be done in 2 (two) steps
• S(n-5) S(n-6) S(n-7) 001
• Step 3.c.4 Preserve Return Address (PC/ IP) in
  relevant stack if necessary
• For CALL Software
  Interrupt Instruction to be done in 2
• (Two) steps. S(n-5)
  S(n-6) S(n-7) 010
• Step 3.c.5 If the Target Address happens to be
  Memory Indirect THEN read that Target Address
  from memory in PC S(n-1)S(n-2) 10 ELSE go
  to Step 3.c.7.
• Step 3.c.6 Calculate 32 bit Linear Address of
  the Target Load PC with it.
• S(n-5) S(n-6) S(n-7) 011 to be
  done in two (2) steps.
• Step 3.c.7 Go to Fetch next Instruction
  S(n-1)S(n-2) 00 .

3
Resolving Memory Indirect Address 1 If
Supported (Single Operand) S(n-1)S (n-2) 10

• 1) MAR? IR (Operand) The MEMORY Address
  Pointer
• S(n-3) S(n-4) S(n-5) S(n-6) 0000 .
• 2) MMU (Offset) ? MAR. MMU (Seg.) ? Data
  Segment (DS)
• S(n-3) S(n-4) S(n-5) S(n-6) 0001 .
• 3) Address Bus ? MMU Memory Read. S(n-3)
  S(n-4) S(n-5) S(n-6) 0010 .
• 4) MDR ? Data Bus Increment MAR S(n-3)
  S(n-4) S(n-5) S(n-6) 0011 .
• 5) MMU (Offset) ? MDR ( The Actual Address)
• . MMU (Seg.) ? Data Segment (DS)
• S(n-3) S(n-4) S(n-5) S(n-6) 0100 .
• 6) Address Bus ? MMU Memory Read. S(n-3)
  S(n-4) S(n-5) S(n-6) 0101 .
• 7) MDR ? Data Bus Increment MAR S(n-3)
  S(n-4) S(n-5) S(n-6) 0110 .

4
Computing Linear Target Address - 1

• Types of Addresses Specified in allowable
  Addressing mode in an Instruction
• 1) Immediate No need to Compute
• 0000 IR (Operand) ? Destination via CPU
  UNI Bus.
• S(n-8) 0 ? Lower Byte. S(n-8) 1
  ? Higher Byte.
• 2) Register Direct No need to Compute.
• IR (Operand) ? GPR File Selection
  (Input/Output).
• 3) Register Indirect
• MAR ? GPR Operand as found in IR S(n-8)
  0
• 4) Memory Direct
• MAR ? IR Operand S(n-8) 0 .

5
Computing Linear Target Address - 2

• Types of Addresses Contd.
• 5) Based Indexed ( rirj ) If Supported
• (i). ALU Op1 ? Base Register Clear CY.
• S(n-8) S(n-9) S(n-10) 000
• (ii) ALU Op2 ? Index Register ADD
• S(n-8) S(n-9) S(n-10) 001
• (iii) Write Result Inhibit ALL Flags
  Except CY.
• S(n-8) S(n-9) S(n-10) 010
• (iv) MAR ? Result. S(n-8) S(n-9) S(n-10)
  011
• N.B Code Segment DS content is to be
  appended to the left.

6
Computing Linear Target Address - 3

• Types of Addresses Contd.
• 6) PC Relative ( /- Offset ) Control Flow
  Instructions (If Supported)
• (i). ALU Op1 ? PC Clear CY.
• S(n-8) S(n-9) S(n-10) 000
• (ii) ALU Op2 ? IR Target Offset ADD
  / SUBTRACT.
• S(n-8) S(n-9) S(n-10) 001
• (iii) Write Result Inhibit ALL Flags
• S(n-8) S(n-9) S(n-10) 010
• (iv) MAR ? Result
• S(n-8) S(n-9) S(n-10) 011
• N.B Code Segment CS content is to be appended
  to the Left.

7
Executing CALL Instruction - 1

• Step 4.a.2 Save / PUSH current IPtr / PC
  (Return Address) in the USER Stack.
• S(n-3)S(n-4) 00.
• a1) Set up Stack Memory Address Assumed SS SP
  already Loaded
• (1) Decrement STACK POINTER (SP).
• (2) MAR ? Stack Pointer USER Stack
  .
• (3) MMU (Offset) ? MAR. MMU (Seg.) ? SS
  USER Stack

8
Executing CALL Instruction - 2

• PUSHING Return Address PC / IP only in
  USER Stack
• (1) Set Up Stack Memory Address As
  illustrated earlier
• (2 ) MDR ? PC / IPTr.
• (3) Address Bus ? MMU Data Bus ?
  MDR Memory Write.
• Nothing else is saved in the USER Stack.
  

9
Executing CALL Instruction - 3

• Compute Linear Target Address ( as illustrated
  already).
• PC ? Target Address.

10
Executing RETURN Instruction

• POPPING Return Address PC / IP only from
  USER Stack
• (1) MAR ? Stack Pointer User Stack
  .
• (2) Increment Stack Pointer.
• (3) MMU (Offset) ? MAR. MMU (Seg. ) ? SS
  USER Stack
• (4) Address Bus ? MMU Memory Read.
• (5) MDR ? Data Bus.
• (6) PC / IPtr ? MDR
• Nothing else is Popped from the USER
  Stack.

11
Executing INTERRUPT Instruction 1A

• Step 3.a.3 Save / PUSH current IPtr / PC
  (Return Address) in the SYSTEM Stack.
• S(n-3)S(n-4) 00.
• a1) Set up Stack Memory Address Assumed SS SP
  already Loaded
• (1) Decrement STACK POINTER (SP).
• (2) MAR ? Stack Pointer SYSTEM Stack
  .
• (3) MMU (Offset) ? MAR. MMU (Seg.) ? SS
  System Stack

12
Executing INTERRUPT Instruction 2A

• PUSHING Return Address PC / IP only in
  SYSTEM Stack
• (1) Set Up Stack Memory Address As
  illustrated earlier
• (2 ) MDR ? PC / IPTr.
• (3) Address Bus ? MMU Data Bus ?
  MDR Memory Write.

13
Executing INTERRUPT Instruction 2A

• Step 3.a.3 Save / PUSH current CS Code
  Segment in the SYSTEM Stack.
• S(n-3)S(n-4) 00.
• a1) Set up Stack Memory Address Assumed SS SP
  already Preset
• (1) Decrement STACK POINTER (SP).
• (2) MAR ? Stack Pointer SYSTEM Stack
  .
• (3) MMU (Offset) ? MAR. MMU (Seg.) ? SS
  System Stack

14
Executing INTERRUPT Instruction 2B

• PUSHING Return Address CS ( Code Segment)
  in SYSTEM Stack
• (1) Set Up Stack Memory Address As
  illustrated earlier
• (2 ) MDR ? CS.
• (3) Address Bus ? MMU Data Bus ?
  MDR Memory Write.

15
Executing INTERRUPT Instruction 3A

• Step 3.a.3 Save / PUSH current PSW Program
  Status Word in the SYSTEM Stack.
• S(n-3)S(n-4) 00.
• a1) Set up Stack Memory Address Assumed SS SP
  already Preset
• (1) Decrement STACK POINTER (SP).
• (2) MAR ? Stack Pointer SYSTEM Stack
  .
• (3) MMU (Offset) ? MAR. MMU (Seg.) ? SS
  System Stack

16
Executing INTERRUPT Instruction 3B

• PUSHING FLAGS r31 in SYSTEM Stack
• (1) Set Up Stack Memory Address As
  illustrated earlier
• (2 ) MDR ? r31.
• (3) Address Bus ? MMU Data Bus ?
  MDR Memory Write.

17
Executing INTERRUPT Instruction 3C

• Step 3.a.3 Save / PUSH current PSW Program
  Status Word in the SYSTEM Stack.
• S(n-3)S(n-4) 00.
• a1) Set up Stack Memory Address Assumed SS SP
  already Preset
• (1) Decrement STACK POINTER (SP).
• (2) MAR ? Stack Pointer SYSTEM Stack
  .
• (3) MMU (Offset) ? MAR. MMU (Seg.) ? SS
  System Stack

18
Executing INTERRUPT Instruction 3D

• PUSHING Last Result r30 in SYSTEM Stack
• (1) Set Up Stack Memory Address As
  illustrated earlier
• (2 ) MDR ? r30.
• (3) Address Bus ? MMU Data Bus ?
  MDR Memory Write.

19
Executing Interrupt Instruction - 4

• Compute Interrupt Vector
• 1a) ALU OP1 ? IR ( Target Vector) Assumed
  only lowest 8 bits are filled All the other bits
  are filled with ZEROES.
• 1b) Logical Shift Left Twice this Content
• ( Multiply by 4).
• 1c) Write Result , Inhibit All Flags.
• 1d) r 30 ? Result.
• 2. PC ? r 30 .

20
Executing IRET Instruction

• POPPING All from SYSTEM Stack in Proper Order.
• (1) MAR ? Stack Pointer SYSTEM Stack
  .
• (2) Increment Stack Pointer.
• (3) MMU (Offset) ? MAR. MMU (Seg. ) ? SS
  SYSTEM Stack
• (4) Address Bus ? MMU Memory Read.
• (5) MDR ? Data Bus.
• (6) (DESIRED DESTINATION) ? MDR

21
Case Study 1

• JZ lt 16 Bit offset Addressgt assumed the higher 16
  bits of the Target Address is already stored as
  ALL Zero in the Instruction itself thereby
  forming a 32 bit Target with Higher 16 Bits ALL
  zero and Lower 16 Bits specified explicitly.
• Assumed this instruction is Already fetched and
  currently lying in the Instruction Register
  itself.
• Step 1 Test ZERO Flag.
• Step 2 If Zero Flag is not set THEN GO TO Step
  3 ELSE if zero flag is set then
• PC / IPtr ? IR (Operand) All 32
  Bits ( Change NEXT Instruction Address ).
• Step 3 Normal Fetch Sequence. MAR ? PC/IPtr

22
Case Study 1 ( Contd.)

• JZ lt 16 Bit offset Addressgt
• New Instruction Fetch
• Step 4 MMU (Offset) ? MAR MMU (Segment) ?
  CS
• Step 5 Address Bus ? MMU Memory Read
  Increment MAR
• Step 6 MDR ? Data Bus.
• Step 7 IR (Op Code) ? MDR
• Step 8 MMU (Offset) ? MAR MMU (Segment) ? CS
• Step 9 Address Bus ? MMU Memory Read
  Increment MAR
• Step 10 MDR ? Data Bus.
• Step 11 IR (Operand) ? MDR

23
Case Study 2

• BEQ ri, rj , lt 16 Bit offset Addressgt assumed
  the higher 16 bits of the Target Address is
  already stored as ALL Zero in the Instruction
  itself thereby forming a 32 bit Target with
  Higher 16 Bits ALL zero and Lower 16 Bits
  specified explicitly.
• Assumed this instruction is Already fetched and
  currently lying in the Instruction Register
  itself.
• Step 1 IR (Operand Portion) ? Register File to
  Select GPR ri
• Step 2 ALU Op 1 ? Selected ri
• Step 3 IR (Operand Portion) ? Register File to
  Select GPR rj
• Step 4 ALU Op 2 ? Selected rj Set Cy ? 0
  Compare / Subtract i
• Step 5 Inhibit Result Writing BUT Set All
  Flags.
• Step 6 Test ZERO Flag.
• Step 7 If Zero Flag is not set THEN GO TO Step
  3 ELSE if zero flag is set then
• PC / IPtr ? IR (Operand) All 32
  Bits ( Change NEXT Instruction Address ).
• Step 8 Normal Fetch Sequence. MAR ? PC/IPtr