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Butterfly circuits

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ilv (bfly (n-1) circ ) - - twoN (n-1) circ. Butterfly. bfly circ ... bfly (n-1) (ilv circ) - - twoN (n-1) circ. And another one. bfly 0 circ = id. bfly n circ ... – PowerPoint PPT presentation

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Title: Butterfly circuits


1
Butterfly circuits
  • more connection patterns

2
Parallel Connection Patterns
G
F
F -- G
3
Working on lists
G
F
parl F G halveList -gt- (F -- G) -gt- append
4
two
two R parl R R
5
two (two R)
6
Many twos
twoN 0 circ circ twoN n circ two (twoN
(n-1) circ)
7
Interleave
R
R
ilv R unriffle -gt- two R -gt- riffle
8
Many interleaves
ilv (ilv (ilv C))
9
Many interleaves
ilvN 0 circ circ ilvN n circ ilv (ilvN
(n-1) circ)
10
Wiring
id2
swap
11
Questions what are
ilvN n id2 ilvN n
swap ?
12
Butterfly
bfly circ
bfly circ
13
Defining Butterfly
bfly 0 circ id bfly n circ ilvN (n-1)
circ -gt- two (bfly (n-1) circ)
14
Questions what are
bfly n id2 bfly n
swap ?
15
Behaviour preserving transformations
two (ilv circ) ilv (two circ) rifflen
identity on size 2n
16
Defining Butterfly again
bfly 0 circ id bfly n circ ilv (bfly
(n-1) circ ) -gt- twoN (n-1) circ
17
Butterfly
bfly circ
bfly circ
18
Yet another view
bfly 0 circ id bfly n circ bfly (n-1)
(ilv circ) -gt- twoN (n-1) circ
19
And another one
bfly 0 circ id bfly n circ ilvN (n-1)
circ -gt- bfly (n-1) (two circ)
20
But they are all the same
  • and even (exercise)

21
Shuffle exchange
22
Butterfly Layout on an FPGA
23
Butterfly Layout on an FPGA
24
Other Transformations
  • Pipelining
  • Serialising parts
  • Playing with space time tradeoffs

25
Sorting (2-sorters)
compUp x,y imin (x,y), imax
(x,y) compDown x,y imax (x,y), imin
(x,y)
26
Note
compUp -gt- swap is same as
compDown compDown -gt- swap is same as
compUp
27
What is the behaviour of
bfly 3 compUp Maingt
simulate (bfly 3 compUp) 1,3,5,7,8,6,4,2 1,2,3,
4,5,6,7,8
28
Another view

Imagine input increasing then decreasing
29
What is the behaviour of
bfly 3 compDown Maingt
simulate (bfly 3 compDown) 1,3,5,7,8,6,4,2 8,7
,6,5,4,3,2,1
30

Imagine input increasing then decreasing
31
A Bitonic Merger (for real)
merger n bfly n twoSorter
merger_top n do inputs lt- inputBus i n
(bit_vector 7 downto 0) clk lt-
globalClock clk ss lt- merger n
inputs outputBus ss s n
(bit_vector 7 downto 0)

32
Recursive Sorter
sorter 0 comp inp inp sorter n
comp inps outs where sortL
sorter (n-1) comp sortR
sorter (n-1) (comp -gt- swapl) merger
bfly n comp outs (parl
sortL sortR -gt- merger) inps
33
sorter 3 compUp

Maingt simulate (sorter 3 compUp)
8,7,1,2,3,4,6,5 1,2,3,4,5,6,7,8
34
sorter 3 compDown

Maingt simulate (sorter 3 compDown)
8,7,1,2,3,4,6,5 8,7,6,5,4,3,2,1
35
sorter description is parameterised on comp (the
2-sorter)
  • have really designed the connection pattern into
    which to plug the
  • 2-sorter from off the shelf
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