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## Algorithmic State Machines Advanced Testbenches

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### Control Unit Example: Arbiter (1) Arbiter. reset. r1. r2. r3. g1. g2. g3. clock ... Control Unit Example: Arbiter (2) ECE 545 Introduction to VHDL. 14 ... – PowerPoint PPT presentation

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Title: Algorithmic State Machines Advanced Testbenches

1
ECE 545 Lecture 6
2
• Stephen Brown and Zvonko Vranesic,Fundamentals
of Digital Logic with VHDL Design
• Chapter 8.10
• Algorithmic State Machine (ASM) Charts
• Chapter 10.2.6
• Sort Operation
• (handouts distributed in class)
• Sundar Rajan, Essential VHDL RTL Synthesis
• Done Right
• Chapter 14, starting from Design
Verification

3
Algorithmic State Machine (ASM) Charts
4
Algorithmic State Machine
• Algorithmic State Machine
• representation of a Finite State Machine
• suitable for FSMs with a larger number of
inputs and outputs compared to FSMs expressed
using state diagrams and state tables.

5
Elements used in ASM charts (1)
State name
Output signals
0 (False)
1 (True)
Condition
or actions
expression
(Moore type)
(a) State box
(b) Decision box
Conditional outputs
or actions (Mealy type)
(c) Conditional output box
6
Elements used in ASM charts (2)
• State box represents a state.
• Equivalent to a node in a state diagram or a row
in a state table.
• Moore type outputs are listed inside of the box.
It is customary to write only the name of the
signal that has to be asserted in the given
state, e.g., z instead of z1. Also, it might be
useful to write an action to be taken, e.g.,
Count Count 1, and only later translate it to
asserting a control signal that causes a given
action to take place.

7
Elements used in ASM charts (3)
• Decision box indicates that a given condition
is to be tested and the exit path is to be chosen
accordingly
• The condition expression consists of one or more
inputs to the FSM.
• Conditional output box denotes output signals
that are of the Mealy type. The condition that
determines whether such outputs are generated is
specified in the decision box.

8
Moore FSM Example 1 State diagram
9
ASM Chart for Moore FSM Example 1
10
Mealy FSM Example 2 State diagram
11
ASM Chart for Mealy FSM Example 2
12
Control Unit Example Arbiter (1)
reset
r1
g1
Arbiter
g2
r2
g3
r3
clock
13
Control Unit Example Arbiter (2)
14
Control Unit Example Arbiter (3)
15
ASM Chart for Control Unit - Example 3
16
Sorting
17
Pseudocode for the sort operation
18
Structure of a Typical Digital System
Data Inputs
Control Inputs
Control Signals
Execution Unit (Datapath)
Control Unit (Control)
Data Outputs
Control Outputs
19
Hardware Design with RTL VHDL
Pseudocode
Execution Unit
Control Unit
Block diagram
Block diagram
ASM
VHDL code
VHDL code
VHDL code
20
Datapath Circuit for the sort operation
21
Control Circuit Part 1
22
ASM chartfor the sort operation
23
ASM chartfor the Control Circuit Part 2
24
VHDL code (1) Entity declaration
• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.components.all
• ENTITY sort IS
• GENERIC ( N INTEGER 4 )
• PORT (Clock, Resetn IN STD_LOGIC
• s, WrInit, Rd IN STD_LOGIC
• DataIn IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• RAdd IN INTEGER RANGE 0 TO 3
• DataOut BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO
0)
• Done BUFFER STD_LOGIC )
• END sort

25
Package components (1)
LIBRARY ieee USE ieee.std_logic_1164.all
PACKAGE components IS -- n-bit register with
enable COMPONENT regne GENERIC ( N
INTEGER 4 ) PORT ( R IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) Resetn IN
STD_LOGIC E IN STD_LOGIC Clock IN
STD_LOGIC Q OUT STD_LOGIC_VECTOR(N-1
DOWNTO 0) ) END COMPONENT
26
Package components (2)
-- up-counter that counts from 0 to modulus-1
COMPONENT upcount GENERIC ( modulus
INTEGER 8 ) PORT ( Resetn IN
STD_LOGIC Clock IN STD_LOGIC E IN
STD_LOGIC L IN STD_LOGIC R IN
INTEGER RANGE 0 TO modulus-1 Q BUFFER
INTEGER RANGE 0 TO modulus-1 ) END COMPONENT
END components
27
Datapath Circuit for the sort operation
28
VHDL code (2) Datapath signal declarations
• ARCHITECTURE Dataflow OF sort IS
• -- datapath data buses
• TYPE RegArray IS ARRAY(3 DOWNTO 0) OF
• STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• SIGNAL R RegArray
• SIGNAL RData STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• SIGNAL ABData STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• SIGNAL A, B STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• SIGNAL ABMux STD_LOGIC_VECTOR(N-1 DOWNTO 0)
• -- datapath control signals
• SIGNAL Rin STD_LOGIC_VECTOR(3 DOWNTO 0)
• SIGNAL IMux INTEGER RANGE 0 TO 3
• SIGNAL Ain, Bin STD_LOGIC
• SIGNAL Aout, Bout STD_LOGIC
• SIGNAL BltA STD_LOGIC

29
Control Circuit Part 1
30
VHDL code (3) Control unit signal declarations
• -- control unit Part 1
• SIGNAL Zero INTEGER RANGE 3 DOWNTO 0
• SIGNAL Ci, Cj INTEGER RANGE 0 TO 3
• SIGNAL CMux INTEGER RANGE 0 TO 3
• SIGNAL LI, LJ STD_LOGIC
• SIGNAL EI, EJ STD_LOGIC
• SIGNAL zi, zj STD_LOGIC
• SIGNAL Csel STD_LOGIC
• SIGNAL Int STD_LOGIC
• SIGNAL Wr STD_LOGIC
• -- control unit Part 2
• TYPE State_type IS ( S1, S2, S3, S4, S5, S6, S7,
S8, S9 )
• SIGNAL y State_type

31
Datapath Circuit for the sort operation
32
VHDL code (4) - Datapath
• BEGIN
• RData lt ABMux WHEN WrInit '0' ELSE DataIn
• GenReg FOR i IN 0 TO 3 GENERATE
• Reg regne GENERIC MAP ( N gt N )
• PORT MAP ( R gt RData,
• Resetn gt Resetn,
• E gt Rin(i),
• Clock gt Clock,
• Q gt R(i) )
• END GENERATE
• WITH IMux Select
• ABData lt R(0) WHEN 0,
• R(1) WHEN 1,
• R(2) WHEN 2,
• R(3) WHEN OTHERS

33
VHDL code (5) - Datapath
• RegA regne GENERIC MAP ( N gt N )
• PORT MAP ( R gt ABData,
• Resetn gt Resetn,
• E gt Ain,
• Clock gt Clock,
• Q gt A )
• RegB regne GENERIC MAP ( N gt N )
• PORT MAP ( R gt ABData,
• Resetn gt Resetn,
• E gt Bin,
• Clock gt Clock,
• Q gt B )
• BltA lt '1' WHEN B lt A ELSE '0'
• ABMux lt A WHEN Bout '0' ELSE B
• DataOut lt (OTHERS gt 'Z') WHEN Rd '0' ELSE
ABData

34
Control Circuit Part 1
35
VHDL code (6) Control Unit Part 1
• Zero lt 0
• OuterLoop upcount GENERIC MAP ( modulus gt 4 )
• PORT MAP ( Resetn gt Resetn,
• Clock gt Clock,
• E gt EI,
• L gt LI,
• R gt Zero,
• Q gt Ci )
• InnerLoop upcount GENERIC MAP ( modulus gt 4 )
• PORT MAP ( Resetn gt Resetn,
• Clock gt Clock,
• E gt EJ,
• L gt LJ,
• R gt Ci,
• Q gt Cj )

36
VHDL code (7) Control Unit Part 1
• CMux lt Ci WHEN Csel '0' ELSE Cj
• IMux lt Cmux WHEN Int '1' ELSE Radd
• RinDec PROCESS ( WrInit, Wr, IMux )
• BEGIN
• IF (WrInit OR Wr) '1' THEN
• CASE IMux IS
• WHEN 0 gt Rin lt "0001"
• WHEN 1 gt Rin lt "0010"
• WHEN 2 gt Rin lt "0100"
• WHEN OTHERS gt Rin lt "1000"
• END CASE
• ELSE Rin lt "0000"
• END IF
• END PROCESS
• Zi lt '1' WHEN Ci 2 ELSE '0'
• Zj lt '1' WHEN Cj 3 ELSE '0'

37
ASM chartfor the Control Circuit Part 2
38
VHDL code (8) Control Unit Part 2
• FSM_transitions PROCESS ( Resetn, Clock )
• BEGIN
• IF Resetn '0' THEN
• y lt S1
• ELSIF (Clock'EVENT AND Clock '1') THEN
• CASE y IS
• WHEN S1 gt IF S '0' THEN y lt S1
• ELSE y lt S2 END IF
• WHEN S2 gt y lt S3
• WHEN S3 gt y lt S4
• WHEN S4 gt y lt S5
• WHEN S5 gt IF BltA '1' THEN y lt S6 ELSE
y lt S8 END IF
• WHEN S6 gt y lt S7
• WHEN S7 gt y lt S8
• WHEN S8 gt
• IF zj '0' THEN y lt S4
• ELSIF zi '0' THEN y lt S2
• ELSE y lt S9
• END IF

39
VHDL code (9) Control Unit Part 2
• -- define the outputs generated by the FSM
• Int lt '0' WHEN y S1 ELSE '1'
• Done lt '1' WHEN y S9 ELSE '0'
• FSM_outputs PROCESS ( y, zi, zj )
• BEGIN
• LI lt '0' LJ lt '0' EI lt '0' EJ lt '0'
Csel lt '0'
• Wr lt '0' Ain lt '0' Bin lt '0' Aout lt
'0' Bout lt '0'
• CASE y IS
• WHEN S1 gt LI lt '1' EI lt '1'
• WHEN S2 gt Ain lt '1' LJ lt '1' EJ lt '1'
• WHEN S3 gt EJ lt '1'
• WHEN S4 gt Bin lt '1' Csel lt '1'
• WHEN S5 gt -- no outputs asserted in this
state
• WHEN S6 gt Csel lt '1' Wr lt '1' Aout lt
'1'
• WHEN S7 gt Wr lt '1' Bout lt '1'

40
VHDL code (10) Control Unit Part 2
• WHEN S8 gt Ain lt '1'
• IF zj '0' THEN
• EJ lt '1'
• ELSE
• EJ lt '0'
• IF zi '0' THEN
• EI lt '1'
• ELSE
• EI lt '0'
• END IF
• END IF
• WHEN S9 gt -- Done is assigned 1 by
conditional signal assignment
• END CASE
• END PROCESS
• END Dataflow

41
Simulation results for the sort operation
42
Simulation results for the sort operation
(2)Completing sorting and reading out registers
43
Alternative datapath based on tri-state buffers
44
45
Using Arrays of Test Vectors In Testbenches
46
Testbench (1)
• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY sevenSegmentTB is
• END sevenSegmentTB
• ARCHITECTURE testbench OF sevenSegmentTB IS
• COMPONENTsevenSegment PORT (
• bcdInputs IN STD_LOGIC_VECTOR (3 DOWNTO 0)
• seven_seg_outputs OUT STD_LOGIC_VECTOR(6
DOWNTO 0)
• )
• end COMPONENT
• CONSTANT PropDelay time 40 ns
• CONSTANT SimLoopDelay time 10 ns

47
Testbench (2)
• TYPE vector IS RECORD
• bcdStimulus STD_LOGIC_VECTOR(3 downto 0)
• sevSegOut STD_LOGIC_VECTOR(6 downto 0)
• END RECORD
• CONSTANT NumVectors INTEGER 10
• TYPE vectorArray is ARRAY (0 TO NumVectors - 1)
OF vector
• CONSTANT vectorTable vectorArray (
• (bcdStimulus gt "0000", sevSegOut gt
"0000001"),
• (bcdStimulus gt "0001", sevSegOut gt
"1001111"),
• (bcdStimulus gt "0010", sevSegOut gt
"0010010"),
• (bcdStimulus gt "0011", sevSegOut gt
"0000110"),
• (bcdStimulus gt "0100", sevSegOut gt
"1001100"),
• (bcdStimulus gt "0101", sevSegOut gt
"0100100"),
• (bcdStimulus gt "0110", sevSegOut gt
"0100000"),
• (bcdStimulus gt "0111", sevSegOut gt
"0001111"),
• (bcdStimulus gt "1000", sevSegOut gt
"0000000"),

48
Testbench (3)
• SIGNAL StimInputs STD_LOGIC_VECTOR(3 downto 0)
• SIGNAL CaptureOutputs STD_LOGIC_VECTOR(6 downto
0)
• BEGIN
• u1 sevenSegment PORT MAP (
• bcdInputs gt StimInputs,
• seven_seg_outputs gt CaptureOutputs)

49
Testbench (4)
• LoopStim PROCESS
• BEGIN
• FOR i in 0 TO NumVectors-1 LOOP
• StimInputs lt vectorTable(i).bcdStimulus
• WAIT FOR PropDelay
• ASSERT CaptureOutputs vectorTable(i).sevSeg
Out
• REPORT Incorrect Output
• SEVERITY error
• WAIT FOR SimLoopDelay
• END LOOP

50
Testbench (5)
• WAIT
• END PROCESS
• END testbench

51
File I/O
52
Design Under Test (1)
• library IEEE
• use IEEE.std_logic_1164.all
• use IEEE.std_logic_unsigned.all
• entity loadCnt is port (
• data in std_logic_vector (7 downto 0)
• clk in std_logic
• rst in std_logic
• q out std_logic_vector (7 downto 0)
• )

53
Design Under Test (2)
• architecture rtl of loadCnt is
• signal cnt std_logic_vector (7 downto 0)
• begin
• counter process (clk, rst) begin
• if (rst '1') then
• cnt lt (others gt '0')
• elsif (clk'event and clk '1') then
• cnt lt data
• else
• cnt lt cnt 1
• end if
• end if
• end process
• q lt cnt
• end rtl

54
Test vector file (1)
• Format is Rst, Load, Data, Q
• load the counter to all 1s
• 011111111111111111
• reset the counter
• 101010101000000000
• now perform load/increment for each bit
• 011111111011111110
• 001111111011111111
• 011111110111111101
• 001111110111111110
• 011111101111111011
• 001111101111111100
• 011111011111110111
• 001111011111111000

55
Test vector file (2)
• 011110111111101111
• 001110111111110000
• 011101111111011111
• 001101111111100000
• 011011111110111111
• 001011111111000000
• 010111111101111111
• 00 0111111110000000
• check roll-over case
• 011111111111111111
• 001111111100000000
• End vectors

56
Testbench (1)
• library IEEE
• use IEEE.std_logic_1164.all
• use ieee.STD_LOGIC_TEXTIO.all
• use std.textio.all

57
Testbench (2)
• architecture testbench of loadCntTB is
• data in std_logic_vector (7 downto 0)
• clk in std_logic
• rst in std_logic
• q out std_logic_vector (7 downto 0)
• )
• end component

58
Testbench (3)
• file vectorFile text is in "vectorfile"
• type vectorType is record
• data std_logic_vector(7 downto 0)
• rst std_logic
• q std_logic_vector(7 downto 0)
• end record
• signal testVector vectorType
• signal TestClk std_logic '0'
• signal Qout std_logic_vector(7 downto 0)

59
Testbench (4)
• constant ClkPeriod time 100 ns
• begin
• -- File reading and stimulus application
• variable VectorLine line
• variable VectorValid boolean
• variable vRst std_logic
• variable vData std_logic_vector(7 downto 0)
• variable vQ std_logic_vector(7 downto 0)

60
Testbench (5)
• begin
• while not endfile (vectorFile) loop
VectorValid)
• next when not VectorValid
• wait for ClkPeriod/4
• testVector.Rst lt vRst
• testVector.Data lt vData
• testVector.Q lt vQ
• wait for (ClkPeriod/4) 3
• end loop

61
Testbench (6)
• assert false
• report "Simulation complete"
• severity note
• wait
• end process
• -- Free running test clock
• TestClk lt not TestClk after ClkPeriod/2
• -- Instance of design being tested
• u1 loadCnt port map (Data gt testVector.Data,
• clk gt TestClk,
• rst gt testVector.Rst,
• q gt Qout
• )

62
Testbench (7)
• -- Process to verify outputs
• verify process (TestClk)
• variable ErrorMsg line
• begin
• if (TestClk'event and TestClk '0') then
• if Qout / testVector.Q then
• write(ErrorMsg, string'("Vector failed
"))
• write(ErrorMsg, now)
• writeline(output, ErrorMsg)
• end if
• end if
• end process
• end testbench

63
Hex format