332:578 Deep Submicron VLSI Design Lecture 10 Design Methodology, Tools, and Flows - PowerPoint PPT Presentation

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Title: 332:578 Deep Submicron VLSI Design Lecture 10 Design Methodology, Tools, and Flows


1
332578 Deep SubmicronVLSI DesignLecture 10
Design Methodology, Tools, and Flows
  • Michael L. Bushnell
  • ECE Department
  • Spring 2005

2
Outline
  • Software Radio Design Example
  • Design Methods
  • Field-Programmable Gate Arrays
  • Design Flows
  • Summary

Material from CMOS VLSI Design, by Weste and
Harris, Addison-Wesley, 2005
3
Software Radio Example
4
Transmit Path IQ Modulator
5
Modulation Methods
  • 2 bits of data encoded in QPSK
  • Typical carrier f 2.4 GHz in Industrial
    Scientific and Medical (ISM) band

6
Receive Path
  • Multiplication, sine wave generation, and
    filtering important

7
Design Principles
  • Hierarchy
  • Regularity
  • Modularity
  • Locality

8
Hierarchy Divide Conquer
  • mprocessor software radio

9
Performance Problems
  • Transmit path needs
  • 2 multiplications
  • 1 addition
  • 2 table lookups (sine cosine)
  • Loop counting 1 more addition
  • Iterative multiply takes N cycles for N-bit word
  • Cycle count 16 16 1 2 2 1 40
  • For 100 MHz processor, leads to
  • 400 ns for IQ conversion
  • By Nyquist criterion, can only generate 1.25 MHz
    IF signal

10
Fixed Function Blocks -- Better
11
Benefits
  • Do 1 addition or multiplication per clock
  • Arithmetic operates at mprocessor clock rate
    100 MHz
  • Due to Nyquist criterion, can now generate IF
    signals at 50 MHz with suitable DAC

12
Regularity
  • Divide hierarchy into set of similar building
    blocks
  • Only a few different blocks
  • Replicate identical blocks to build larger units
  • Example NCO (numerically-controlled oscillator)
  • Registered adder increments every clock cycle
    by phase increment register
  • Phase counter steps through Sine ROM lookup
    table to provide phase-to-amplitude conversion
  • Add in phase offset to phase incrementer to do
    phase modulation

13
Phase Modulator
14
Finite Impulse Response Filter
15
Modularity
  • Modules need well-defined functions and
    interfaces
  • Clear behavioral, structural, and physical
    interface
  • Function
  • Ports
  • Name
  • Signal type
  • Input, output, bidirectional, power, ground,
    analog or digital
  • Electrical timing constraints on ports
  • Inputs should only drive transistor gates
  • Not diffusion terminals
  • Physical interface position, layer, width

16
Locality
  • Other than specified interfaces, module internals
    unimportant to other modules
  • Information hiding reduce apparent complexity
    of module
  • Dont use global hardware variables
  • Temporal locality or adhere to a clock/timing
    protocol
  • Reference all signals to a clock
  • Inputs have setup and hold times
  • Output delays are relative to clock edges
  • Use physical locality

17
Software Radio Floorplan
18
Better Floorplan
  • Shorter bus

19
Hardware/Software Parallels
20
Design Methods
  • Microprocessor/DSP
  • Programmable Logic
  • Field-Programmable Gate Arrays
  • Gate Array and Sea-of-Gates
  • Cell-Based Design
  • Full Custom Design
  • System-on-a-Chip

21
Microprocessors
  • Many come with built-in RAM and EEROM/EPROM
  • Some come with analog-to-digital converters
  • Software development costs can be high
  • Suppliers ARM, MIPS, IBM PowerPC

22
Programmable Logic
  • Use when cost, speed, or power of mprocessor
    unacceptable
  • Programmable Logic Arrays
  • Has AND plane and OR plane
  • Can program each transistor to be present or not
  • Fusible link
  • EEROM transistor
  • RAM Cell
  • Realized with NOR-NOR structure
  • Chips with programmable interconnect
  • Chips with reprogrammable logic interconnect

23
PLA Structure
24
Field-Programmable Gate Arrays
  • Two Kinds
  • Use fuse or antifuse permanently programmed
    logic (Actel)
  • Field-programmable
  • Use static RAM cells to customize routing logic
    functions

25
Programmable Interconnect
26
Actel FPGA
  • LM logic module
  • 82 K to gt 1 million logic gates

27
Xilinx FPGA
  • CLB configurable logic block

28
FPGA Logic Cell
  • 16 x 1 static RAM for truth table

29
Optimizations
  • Multiple dedicated clock lines
  • Fast arithmetic blocks
  • Dedicated RAM blocks
  • High-speed I/O interfaces
  • Embedded RISC microprocessors
  • Xilinx XCVP125 FPGA
  • 125,000 logic cells (7 million 2-input gates)
  • 4 RISC processors
  • Multi-gigabit I/O
  • More than 1000 user-available I/O pads

30
FPGA Crossbar Router
31
FPGA Routing Cell
32
Example Personalized FPGA
33
FPGA Summary
  • Best choice for low to medium-volume custom logic
  • Extremely high densities of reprogrammable logic
    gates at low cost
  • Compared to conventional ICs
  • Slower
  • Much more chip area
  • Much more power usage
  • Moderate to high cost/part
  • Initial manufacturing costs of custom ICs
    increasing
  • FPGA cost decreasing
  • Makes FPGA attractive more low to mid-volume jobs

34
Gate Arrays and Sea of Gates
  • Construct common base transistor array
  • Personalize with unique metal and via masks
  • Vendors stock base wafers processed up through
    poly
  • Low cost
  • Many different chips use same base wafer
  • Low processing time for a few metal layers
  • Standard packages and pinouts
  • Reuse common test fixtures
  • Example LSI Logic RapidChip technology
  • Integrated RISC core, 20 million gates, 10 Mbits
    of RAM, 4.25 Gbps I/O, clock of 300 MHz

35
Differences
  • Sea of Gates
  • Continuous array of transistors
  • Separate transistors by pulling poly line of nMOS
    to Ground, poly line of pMOS to VDD
  • Gate Array
  • Non-continuous transistor array
  • Not all transistors have the same size
  • Both are better than FPGAs
  • Less power
  • Lower cost in volume production

36
Sea-of-Gates Cells
37
Gate Array Cells
38
SOG Floorplan
39
SOG 3-Input NAND Gate
40
Gate Array 3-Input NAND
41
Standard (Sandia) Cells
  • Fixed height (pitch)
  • Width varies with gate function
  • Automatically placed in rows and wires routed by
    Cadence Envisia tool (silicon ensemble)

42
Example Standard Cell
43
Standard Cell Layouts
44
Standard Cell Layouts
45
Design Method Comparison
46
Design Method Comparison
47
Design Decision Tradeoffs
48
Generalized Design Flow
49
RTL Synthesis Flow
50
Verification
  • Rerun test benches and make sure they give
    identical results for both behavioral and logic
    simulation
  • Run a formal verification program proves
    equivalence of behavior and logic descriptions
  • Check that all bus assignments match in width
  • Make sure that all outputs are connected

51
Static Timing Analysis
  • Quick and exhaustive
  • Inputs
  • Netlist
  • Logic gate delays (from library)
  • Estimated routing loads
  • Clock period
  • Check for both min-delay and max-delay
  • Easily fooled by false paths in circuit
  • Calculate earliest and latest signal arrival
    times at all logic gates in circuit

52
Test Scan Register Insertion
53
Standard Cell Place Route
54
Standard Cell Layout
55
Timing-Directed Placement
56
Mixed-Signal/Custom Flow
57
Programmed Behavioral Synthesis
58
Summary
  • Software Radio Design Example
  • Design Methods
  • Field-Programmable Gate Arrays
  • Design Flows
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