Chirayu Amin chirayu's'aminintel'com Chandramouli Kashyap Noel Menezes Kip Killpack Eli Chiprout

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A Multi-port Current Source Modelfor Multiple
Input Switching Effectsin CMOS Library Cells

• Chirayu Amin (chirayu.s.amin_at_intel.com)Chandramou
  li KashyapNoel MenezesKip KillpackEli Chiprout

Design Automation Conference, 2006
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Outline

• Motivation
• Multi-port Current Source Model (MCSM)
• Cell Library Characterization
• Timing Analysis
• Results
• Conclusions

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Timing Analysis is a major problem
waveform
RC
0
load
ceff
x-cap

• Process is not scaling as desired
• Guard-banding is unaffordable

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Multiple Input Switching (MIS)
a
b
out

• MIS ? large delay and slew push-out (pull-in)

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Receiver Modeling
Load Linearization
a
b

• Linearization ? large slew errors
• Errors accumulate on a path

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Related WorksWaveform and Load Dependent Models

• Linear Thevenin Driver (default)
• CCSM (Synopsys), ECSM (Cadence)

delay f(slew,Cload)
rd
Vout
Iout f(slew,Cload)
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Related WorksWaveform and Load Independent
Models

• Croix and Wong, DAC 2003
• Keller et al, ICCAD 2004
• Li and Acar, ICCD 2005

Iout f(vin,vout)CLinear
Iout f(vin,vout) CLinear and CMiller
Iout f(vin,va) Cout g(vin,va) 2-pole for input
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MCSM - A Comprehensive Model

• Related CSMs do not completely address
  high-performance libraries

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Outline

• Motivation
• Multi-port Current Source Model (MCSM)
• Cell Library Characterization
• Timing Analysis
• Results
• Conclusions

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Roots of MCSM
MOSFET
I fS(vD,vG,vS,vB)QgS(vD,vG,vS,vB)
I fD(vD,vG,vS,vB)QgD(vD,vG,vS,vB)
MOSFET Model
Nonlinear Capacitances CDS ?QD/?vS, CGS
?QG/?vS, etc.

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From MOSFETs to an Inverter
out
in
Iout fout(vin,vout)Qoutgin(vin,vout) Cout-in?
Qout/?vin and so on

• Inverter MCSM is a cell-level extension of the
  MOSFET model

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MCSM for other cell types

• Nonlinear current source and nonlinear
  capacitor for every pin

Io fo(va,vb,vo) Qogo(va,vb,vo) Cao ?Qa/?vo
and so on
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Outline

• Motivation
• Multi-port Current Source Model (MCSM)
• Cell Library Characterization
• Timing Analysis
• Results
• Conclusions

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Cell Library Characterization
How do we go from netlists
to MCSMs?
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DC Current Source (i) Characterization

• Independent of input waveforms or loads

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Charge (Q) CharacterizationImportance of
Preserving Nonlinearity
gt10slew error

• Linear capacitance approximation cannot match
  both delay and slew
• Croix and Keller CSMs do not capture nonlinearity

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Charge (Q) Characterization
integral

• Independent of input waveforms or loads

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Characterization Complexity

• Storage
• n-dimensional look-up tables (equations may also
  be used)
• n number of pins
• Implemented using look-up tables
• Linear interpolation
• Characterization Runtime
• O(mn) DC simulations and O(mn) transient
  simulations
• m of samples between Vdd and Gnd
• Inverter ? 10 seconds
• 2-input cell ? lt1 minute
• 4-input cell ? 5 minutes on a 3 GHz machine

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Outline

• Motivation
• Multi-port Current Source Model (MCSM)
• Cell Library Characterization
• Timing Analysis
• Results
• Conclusions

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Timing Analysis

• Simulation-based approach

Cload

• Nonlinear circuit simulation

MCSM
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MIS and Nonlinear Loading

• Simulation based approach
• Use exact offsets and waveforms for MIS
• Use MCSM as a nonlinear receiver model

Nonlinear receiver
Nonlinear driver
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MCSM Runtime

• Major speed-up over circuit simulation
• Original netlist many transistors and diodes,
  hundreds of resistors and capacitors
• MCSM a few current sources and capacitors
• Typical Speedup ? 50 to 100X over fast,
  table-based circuit simulator

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Outline

• Motivation
• Multi-port Current Source Model (MCSM)
• Cell Library Characterization
• Timing Analysis
• Results
• Library-level Accuracy Studies
• Microprocessor Block Studies
• Conclusions

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Library-level Accuracy Studies

• MCSM Characterization
• Large portion of our cell library (single-CCC
  cells)
• 65 nm CMOS, extracted cell netlists
• Monte Carlo with 5000 samples
• Additional variation of input offsets for MIS
• Compare MCSM with transistor-level analysis
• Delay and output slew comparison

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Single Input Switching An Example2-input nand
gate
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SIS Delay and Slew Errors
MCSM vs. Transistor-level simulation
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Multiple Input Switching An Example2-input nand
gate
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MIS Cell Delays and Slews
MCSM vs. Transistor-level simulation
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Microprocessor Block Studies(65 nm CMOS)

• Extracted stages
• Driver Interconnect Receivers
• Compare MCSM with transistor-level analysis
• Input waveforms from transistor-level analysis
• Delay and output slew comparison
• Additional experiments
• MCSM for MIS modeling
• MCSM for receiver modeling

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Stage Errors MCSM for SIS Modeling
MCSM vs. Transistor-level simulation
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Stage Errors MCSM for MIS Modeling

• Not modeling MIS ? large errors (up to 150)

MCSM vs. Transistor-level simulation
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Stage ErrorsMCSM for Nonlinear Receiver Modeling

• Linear receiver model ? -30 error in slew

MCSM vs. Transistor-level simulation
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Conclusions

• MCSM handles MIS and receiver modeling
  accurately
• MCSM is 50-100x faster on average than fast,
  table-based circuit simulation
• MCSM has the potential to handle x-caps, power
  supply variations, and other complex effects
• Because it is simulation based

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Acknowledgements

• Rafael Rios
• Marek Patyra
• Avi Efrati
• Haydar Kutuk
• Moshe Kleyner