Source: A New Enhanced Approach to Technology Mapping By Alan Mishchenko

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AIG An Efficient Boolean Network Representation

• Source A New Enhanced Approach to Technology
  Mapping - By Alan Mishchenko
• Name Shruti Vyas
• Date 04/30/09

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Overview

• Introduction
• Motivation
• AIG Rewriting
• Mapping Flow for ASIC with AIGs
• Mapping Flow for FPGA with AIGs
• Conclusions
• References

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Introduction

• AND Inverter Graph is a DAG that represents
  structural implementation of logical
  functionality of a circuit in the form of two
  input AND gates and inverters
• AIGs are not canonical
• FRAIGs (Functionally Reduced AIGs) are
  semi-canonical
• AIGs can be constructed from SOP, BDD or a
  Boolean Network
• AIGs are used for both combinational and
  sequential circuits
• Applications Formal Verification(CEC and BMC),
  Logic Synthesis, Lossless Logic Synthesis and
  Technology mapping
• Tool used for AIG construction - ABC

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Motivation behind AIG

• Boolean Networks Not completely structural and
  uniform
• BDDs Their canonicity forces their size to
  be exponential for circuits like multipliers
• SOPs Two level form leads to non-robust
  manipulation of large logic nodes
• Boolean representation and computation is more
  robust with AIGs than BDDs
• AIGs are uniform since they consist of only AND
  gates and inverters
• Time and size is proportional to the size of the
  circuit

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Some Definitions

• A circuit is represented by an Object Graph
• The gates are represented by a Subject Graph
• The function of a cut is the Boolean function of
  the root of the cut expressed in terms of the
  leaves
• The level of a node is the length of the longest
  path from any PI to the node
• A Cut C for node n is a set of nodes, such that
  every path from the PI nodes contains a node
  belonging to C
• Two circuits are N Equivalent if one function can
  be obtained from another by selectively
  complementing the inputs of the cut
• Phase assignment selects polarities of the inputs
  of cut to minimize the arrival time of the output

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AIG non-canonical

• Canonical A representation of a Boolean
  function is canonical if the representation is
  unique
• AIGs are non-canonical since the same function
  can be represented by two functionally equivalent
  AIGs with different structure

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AIG vs FRAIG

• FRAIG An AIG with no pair of nodes representing
  the same function i.e. AIG without any
  functionally redundant nodes
• For any pair of nodes A and B, fA(a,b,c)!fB(a,b,c
  )
• Use functional reduction algorithm to convert AIG
  to FRAIG. Reference2
• Note Recall ROBDD

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AIG Rewriting

• f abc
• Case1 Subgraph 1 substituted by Subgraph 2
• Case2 Subgraph 2 substituted by Subgraph 1
• Functional matching preferred over structural
  matching
• DAG aware mapping is followed
• Refactoring and Balancing are some other AIG
  rewriting techniques
• AIG rewriting reduces area and delay by about
  10-20
• Reference4

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The Mapping Flow for ASIC

• Create the starting AIG Graph
• Compute all k-feasible cuts for each node
• Perform Boolean matching between the functions of
  cuts and the library gates
• Map the internal nodes
• Select delay optimal mapping
• Post-process to recover area

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Create Starting AIG

• AIGs are constructed from the boolean network and
  are reduced to FRAIGs so that the AIG size is
  minimized and its almost canonical
• Constructed from the netlist available from
  technology independent logic synthesis

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Compute K-feasible Cuts (1/2)

• Node n is the root of cut
• Nodes in the set are the leaves of C
• Nodes between root and leaves are internal nodes
• Size of the cut C is the number of nodes in C
• Cuts computed from PO to PI

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Compute K-feasible Cuts (2/2)

• Cutset initialized to empty
• Merged cut is union of nodes belonging to the
  generating cuts
• If size of cut doesnt exceed k and its
  encountered for the first time, it is added to
  resulting cut set

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Boolean Matching (1/2)

• After computing k feasible cuts, these cuts are
  implemented using gates from the library
• Avoid structural matching
• Table 2 represents truth tables for different
  phases of inputs
• Phase 001 is selected as the N-canonical form of
  f and it represents the entire class
• f1 and f2 are not N equivalent
• f1 and f3 are N equivalent

Number of variables 3 Length of bit stream in
truth table 23 8 c1 c2 c3 represent phases
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Boolean Matching (2/2)

• All boolean functions are divided into
  N-equivalent classes with a representative for
  each class
• In the pre-computation phase, a hash table is
  created for the technology library storing the
  truth tables and N-canonical forms of all the
  gates present in the library
• The canonical form is used to find the set of
  gates which can implement the cut
• Boolean Matching done for cuts in arbitrary order
• Technique used since AIGs are non-canonical

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Mapping Internal Nodes (1/2)
3 Feasible Cuts
2 Feasible Cuts
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Mapping Internal Nodes (2/2)

• Procedure NodeComputeMapping selects the cut with
  earliest arriving output to implement the node,
  area used as tie breaker
• Procedure CutComputeArrivalTime computes arrival
  time of a cut which takes the results of Boolean
  Matching step namely the set of gates with their
  phase/polarity
• The dual-rail mapping (Truth Table for cut and
  its complement) gives the best arrival time of
  the positive and negative phases of the node

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Delay Optimal Mapping

• One of the two polarities of the node, positive
  or negative, is selected using the arrival times.
  An inverter might be added to invert the polarity
• The selected cut and its phase transformation are
  retrieved
• The same procedure is called recursively for the
  fanins of this cut, which are needed in the
  polarity given by the transformation phase
• Finally, the optimal delay cut and its polarity
  are stored at the node

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Recovering Area

• Efficient area recovery techniques not yet
  implemented
• Possible approaches are
• Iterative minimization of area flow
• Incremental re-synthesis through symbolic
  substitution
• These techniques should recover area without
  increasing the circuit delay

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Mapping Flow for FPGA

• Step 12 AIG creation and K-feasible cut
  generation steps remain unchanged
• Step 3 Boolean matching doesnt require truth
  tables and N-canonical forms. LUT matches a cut
  if leaves of cut lt inputs of LUT
• Step 4 Arrival time(k-input cut) max arrival
  time(cut inputs)delay(k-input LUT). Cut with
  minimum arrival time is selected
• Delay optimal mapping in which both phases of
  each node are mapped, is not required
• Process goes from POs to PIs
• Finally the complete object graph is covered with
  LUT blocks. This delay-optimal cover might
  require area recovery

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Conclusions

• AND Inverter Graph is a fast and efficient
  approach of technology mapping
• Combines boolean and algebraic methods
• Algebraic decomposition to construct starting
  object graph
• Boolean transformations to increase the mapping
  choices
• Reduces run time by fine-tuning implementation
  and relying on pre-computation
• Gives results as good as being a canonical form
  though it is not
• Future work Exploring the role of dont cares
  in Boolean Matching

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References

• Alan Mishchenko, A New Enhanced Approach to
  Technology Mapping
• Alan Mishchenko, Roland Jiang, Satrajit
  Chatterjee, Robert Brayton, FRAIGs A Unifying
  Representation for Logic Synthesis and
  Verification
• Alan Mishchenko, Roland Jiang, Satrajit
  Chatterjee, Robert Brayton, FRAIGs Functionally
  Reduced AND-INV Graphs
• Alan Mishchenko, Roland Jiang, Satrajit
  Chatterjee, Robert Brayton, DAG-Aware AIG
  Rewriting, A Fresh Look at Combinational Logic
  Synthesis
• http//gauss.ececs.uc.edu/Courses/C626/Lectures/AI
  G/std.pdf

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Questions

• Thank you for listening!