CRIC and clock

1
CRIC and clock control
CRIC is a front-end CCD Readout Integrated
Circuit Low noise, low power, wide dynamic range,
multi-gain Clock and control is used to move
charge on CCD Well behaved clock is very important
2
Requirements

• Low noisePhotometry CCD electronic noise ?
  4e rms (14mV)Spectrograph CCD electronic
  noise ? 2e rms (7mV)
• Large dynamic range96dB from noise floor to
  130ke well depth (16-bit)
• Readout frequency ? 100 kHz 50kHz
• Radiation tolerant 10 kRad ionization (well
  shielded)
• Low power ? 200mJ/image/channel gt 10mW/channel
• Operation at 140K and 300KAllow normal operation
  at 140K and chip testing at room temperature
• Compact
• Robust, space qualified

Specs exceed sky noise that dominate DECam
See JP Walder presentation at NSS 2003!
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Noise on the CCD Sensor

• Correlated double sampling removes reset
• level and the kTC noise and reduces 1/f noise.
• Integration reduces the thermal noise.

4
Single CRIC Channel
CCD conversion gain 3.5mV/e
C
Switch matrix
Out
R
Vn
R1
R2
A3
Vout
R1
Vn
R2
-
R
-
A1
A2
(CDS)

Out-

Vn
C
CCD noise source
Out
(t4ms)
t
t
time
Reset integration
Signal integration
Real integration during 2t. Good rejection of the
CCD thermal noise.
5
Multi-ranging is built-in
Poisson ? electronic noise
6
Simulation results
Full scale signal simulation at 100kHz readout
rate
Gain 2 Indicator bit
Gain 1 Indicator bit
Output signal
7
Actual device

• Fabricated test chip (no-ADC)
• Four channels and test structures
• Good results with testing so far
• Next version submitted in March has ADC

Good linearity and noise
8
Comments

• CRIC chip is actively being developed for use
  with SNAP CCDs
• I personally think its a no-brainer to use this
  device for analog-to-digital on the focal plane
• Power is low and plans for packaging have a CRIC
  board
• Clock and control is open as to whats on the
  focal plane and whats not

9
Cost and schedule
exists
1K/chip
100K
H. Von der Lippe
Other cost savings possibilities exist