HCAL Tridas SLHC

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HCAL Tridas SLHC
Drew Baden University of Maryland February 2004
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Parameters

• Just to be sure Im on the right page...
• SLHC Bx 80MHz
• Level 1 will run at 80MHz
• Vitesse links upgraded
• TPG data to Level 1 at 2x current speed
• Same 100kHz L1A rate
• Questions
• What will be the L1 latency?
• Same latency in time?
• We like it ? but wed like it to increase!
• Same latency in clock ticks?
• Disaster ?
• Any anticipated changes to TTC?
• What will HCAL build anyway?

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HCAL in SLHC FE and Clocking

• With current technology
• HCAL HB/HE Front-end needs no changes, so
• HCAL could keep same FE boards and same GOL
  1.6Gbaud links
• We already integrate over 2 buckets for Bx
  40MHz
• In HTR, associate energy with beam crossing
  number for TPG and DAQ paths
• Use a simple peak finding algorithm (up/down
  over 3 successive buckets)
• More on this later
• HF FE might need some changes (signal is too fast
  for 40MHz front-end)
• HCAL synchronization/clocking scheme
• Current clocking scheme
• Very versatile, will accommodate current 40MHz
  running
• See Chris Tullys talk

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Timing signals - Overview
Low-skew clock distribution tree dedicated to the
Trigger Primitives output (SLB)
Fanout Card (in GLOBAL mode)
Unique board for HCAL and possibly ECAL
This scheme allows 18 TPG crates. Is it enough ?
Depends also on ECAL. Otherwise need one more
layer.
Rack-to-Rack CAT 7

Fanout Card (in CRATE mode)
Fanout Card (in CRATE mode)
Fanout Card (in CRATE mode)
One board per TPG crate

VME get histograms results and adjust timing
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Fanout board (2 operating modes Global or Crate)
TTCrx
TTC fiber
40MHz
QPLL can run stand-alone
Clk80
QPLL
18 Outputs
RX_CLK 40MHz
INT_BC0
FPGA
RX_BC0
EXT_BC0
Delay
RX_CLK 40MHz
Input from GLOBAL Fanout
RX_BC0
EXT 80MHz
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Complete path of a 40MHz RX_CLK
Fanout board in Global-mode
TTCrx
CLK40_Des1
TTC fiber
3.3V CMOS

• Path is 3.3V differential PECL unless otherwise
  stated.
• Path of RX_BC0 is similar but comes from the
  FPGA rather the QPLL
• In the Global-mode card, do not mount the
  buffers for CLK80 and TTC

QPLL
FPGA
CAT7 (RX_CLK,RX_BC0)
CAT7 (RX_CLK, RX_BC0, TTC, CLK80)
TTCrx
QPLL
Spec is Skew lt ? 12 ns across HCAL and ECAL
FPGA
Fanout board in Crate-mode
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HCAL TPG Current 40MHz Scheme
Fiber Data
Serial Optical Data
Princeton Fanout Card (1/VME crate)
Deserializers (8)
LC
Ref Clk
Crate80
20
Recovered Clk
TTCrx
TTC
TPGBC0
TPG40
PLL
TTC40
x2
SLB
SYS80 Clk
TTC Broadcast
SLB
Princeton Fanout Card (GLOBAL)
SLB
SYS40 Clk
TPG Path
HCAL
SLB
XILINX
SLB
SLB
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HCAL in SLHC HTR/SLB

• Changes to HTR for 80MHz running
• HB/HE tower energy takes 50ns to be collected
• For 80MHz, adopt a more complicated peak finding
  algorithm
• Use weighted filter to associate energy with
  crossing
• Need some simulation effort here to study how
  best to do this
• Will require more cycles inside FPGA
• Current measurements 12 ticks (_at_40MHz) now
• _at_80MHz, 2x will probably not be enough
• This is where an increase in Latency TIME is
  critical
• Will current Xilinx Virtex2 3000s work _at_ 80MHz?
• Probably yes currently only 50 logic used,
  80MHz is not overly fast
• Can we send data to SLBs at twice the rate?
• Probably yes HTR layout was done by hand with a
  lot of care
• Need to test this on production boards sometime
  this year

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HCAL in SLHC HTR/SLB (cont)

• Can we use the same HTRs for 80MHz running?
• Probably yes. Depends on results of
• Simulation/testbeam data analysis to study 12.5ns
  filtering schemes
• Results of tests on Rev4 HTRs (appearing now) on
  SLB connectivity
• Results of efforts to constrain phase differences
  for sychronization
• See Chris Tullys talk
• Note increase in L1 latency will be necessary

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Improvements to Level 1

• Assumption Level 1 will need 2xTPG transmission
  rate
• If so, we will need to rebuild the SLBs
• Consider whether an increase of latency can be
  put to good use here
• Preprocess TPG before sending to Level 1?
• Extend real jet triggers to forward region (HF)
  could be done soon as at test
• Perhaps finer granularity, jet isolationask
  Tully!
• Consider a joint HCAL/ECAL solution.

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Current HCAL/ECAL System
Level 1 Pipeline

• ECAL
• Data sent to Trigger Concentrator Card (TCC)
  using fiber G-Link
• TCC sends data to RCT via SLBs and copper cables
  running at 1.2Gpbs
• Data is buffered in the Front End
• HCAL
• Data buffered in the HTR
• Sent to the RCT via SLBs, just like ECAL

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First part of Upgrade

• Focus on ECAL and HCAL commonality via SLB
• Proposal
• New board Calorimeter Synch Board (CSB) (and L1
  preprocessor)
• Replace SLBs with passive high rate transmitter
  cards (G-link?)
• Send raw HCAL data from HTR to new board
• No need for compression inside HTR frees up
  BRAM and logic
• Accept fiber TPG data from HCAL (and ECAL)?
• Implement SLB functionality on a single card
• Send data from CSB to RCT via mezzanine
• Could use Vitesse copper for compatibility with
  current system
• Could use Fiber serial output
• Would need few of these (compared to SLBs)
• Could accept both ECAL and HCAL data on same
  boardfood for thought

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CSB Schematic

• Fiber input
• Gigabit or G-link
• G-link accommodates ECAL
• Channel count
• At least 48 for HCAL
• Enough channels to do summing if used by ECAL
• Output
• Via mezzanine sites
• Can build small vitesse cards to use with current
  RCT
• Can use Fiber for possible future upgrades to RCT
• Use FPGA with built-in serializer
• Current ones have too much latency investigate?

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CSB

• 9U board with fiber inputs
• FPGAs to implement SLB functionality
• Histogramming, synchronization, etc
• Mezzanine for output to RCT
• Can make small vitesse transmitters, or replace
  with faster optical in the future
• Added bonus
• Do some preprocessing to offload some of the
  stuff RCT does now
• Save a few clock ticks in latency due to
  integration
• Offload some of the HTR work might make it able
  to run at 80MHz?
• Level 1 pre-processing (depends on ECALmore in
  subsequent slides)
• Possibility of adding EMF, isolation, etc. to TPG
• Level 1 preprocessing
• Virtex 2 Pros have built-in Motorola processors
• Can do monitoring, etc.
• Ethernet access via front-panel
• DAQ path for the TPG path
• Implement jet triggers in forward direction?

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Who?

• Maryland (Baden etal)
• University of Virginia (Hirosky)
• Princeton (Tully, Marlow)
• Prototype card for HO mTrigger

Fiber input
Copper inputs
Virtex2Pro built in serdesPPC computer
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Fun

• Can we think up a new Level 1 architecture?
• CMS pipeline contains a certain number of events
• Current trigger is a pipelined processor
• Level 1 chews on all n events in the pipeline
  simultaneously
• Could we instead consider building a farm of
  n processors to chew on 1 event at a time, at
  least for the calorimeter trigger?

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Asynchronous Level 1
Here we need to put the L1 answers back into a
synchronous stream.