Floorplan Evaluation with TimingDriven Global Wireplanning, Pin Assignment and Buffer Wire Sizing

1
Floorplan Evaluation with Timing-Driven Global
Wireplanning, Pin Assignment and Buffer / Wire
Sizing
Christoph Albrecht Synopsys, Inc., Mountain
View formerly Research Institute for
Discrete Mathematics, Bonn, Germany Andrew B.
Kahng, Ion Mandoiu UC San Diego, La
Jolla Alexander Zelikovsky Georgia State
University, Atlanta
ASPDAC 2002, Bangalore
2
Outline

• Previous Work
• Buffer Block-/ Site-Methodologies
• Floorplan Evaluation Problem
• Key Ingredient Gadgets
• Multicommodity Flow Approximation
• Algorithm / Randomized Rounding
• Experimental Results

3
Previous Work

• Floorplan
• Chen et al. BBL VLSI83, Dai et al.
  TCAD87,
• Cong TCAD91
• Buffer Block Methodology
• Cong et al. ICCAD99, TangWong ISPD00
• Buffer Site Methodolgy
• Alpert et al. DAC01
• Multicommodity Flow Approximation Algorithm
• Garg and Konemann FOCS98
• Fleischer SIDMA00
• Application to Global Routing
• Albrecht ISPD00 TCAD01
• Application to Buffer Block Methodology
• Dragan et al. ICCAD00 ASPDAC01 WADS01

4
Buffer-Block Methodology
Cong et al. ICCAD99, TangWong
ISPD00, Dragan et al. ICCAD00 ASPDAC01

• Buffers inserted in blocks located within
  available free space
• Simplifies design by isolating buffer insertion
  from circuit block implementations

5
Buffer-Site Methodology
Alpert et al. DAC01

• Block designers leave holes in circuit blocks
  to be used for buffer insertion
• Alleviates congestion problems of buffer blocks

6
Buffer-Site Methodology
Alpert et al. DAC01

• Block designers leave holes in circuit blocks
  to be used for buffer insertion
• Alleviates congestion problems of buffer blocks

7
Buffer-Site Methodology
Alpert et al. DAC01

• Block designers leave holes in circuit blocks
  to be used for buffer insertion
• Alleviates congestion problems of buffer blocks

8
Floorplan Evaluation Problem
Given

• Tile graph G to model congestion
• wire capacity w(u,v) number of free routing
  channels between tile u and v.
• buffer capacity b(v) possible number of
  buffers in tile v.
• Netlist (source and sink pins given as sets of
  tiles)
• Maximum wireload of buffers / sources U

9
Floorplan Evaluation Problem
Given

• Tile graph G to model congestion
• wire capacity w(u,v) number of free routing
  channels between tile u and v.
• buffer capacity b(v) possible number of
  buffers in tile v.
• Netlist (source and sink pins given as sets of
  tiles)
• Maximum wireload of buffers / sources U

Find
Pin assignment and feasible buffered routing for
nets, subject to buffer and wire congestion
constraints and minimizing the total routing
area, ?(buffers) ?(total wirelength),
where ?, ? ? 0 are given scaling constants
10
Key Ingredient Gadgets
Tile graph G
11
Key Ingredient Gadgets
12
Key Ingredient Gadgets
13
Key Ingredient Gadgets
Lemma 1-to-1 correspondence between feasible
buffered paths for net N in G and s t
paths in H.
i
i
i
14
Integer Program
(
)



å
å
å

a
Ç

Ç
b
x
E
p
E
p
min
p
v
u
v
,
p
v
u
v
)
,
(


å
Î
"

Ç
G
V
v
v
b
x
E
p
)
(


),
(
µ

s.t.
p
v
0
p


å
Î
"

Ç
G
E
v
u
v
u
w
x
E
p
)
(
)
,
(


),
,
(
?

p
v
u
0
,
p
å
"

x
net





,
1

p
p
"
Î
p
x
path

feasible




0,1,

p

15
Integer Program
(
)



å
å
å

a
Ç

Ç
b
x
E
p
E
p
min
p
v
u
v
,
p
v
u
v
)
,
(


å
Î
"

Ç
G
V
v
v
b
x
E
p
)
(


),
(
µ

s.t.
p
v
0
p


å
Î
"

Ç
G
E
v
u
v
u
w
x
E
p
)
(
)
,
(


),
,
(
?

p
v
u
0
,
p
å
"

x
net





,
1

p
p
"
Î
p
x
path

feasible




0,1,

p
Linear Relaxation
³
x


0
p
16
Dual Linear Program
å
l
max
i
i
å
å

v
b
y
)
(
µ

s.t.


v
u
w

)
,
(
?
D u
1
v
0
0
v
u,v
(
)



å
a
u

Ç
y
E
p

v
v
v
(
)

å
z

³

u
b
Ç

l
E
p
u,v
i
v
u
,
v
u
,
"
p
path
Î
"
G
V
v
)
(

³
y


0
v
Î
"
³
G
E
v
u
)
(
)
,
(

z

0
u,v
17
Solution
Linear Relaxation Multicommodity flow with set
constraints Garg and Konemann
FOCS98 Fleischer SIDMA00 Randomized
Rounding Raghavan Thomson COMB87
18
Approximation Algorithm
xp0, yv?/?0b(v), ze?/?0w(e), u?/D, pi? While
?v b(v)yv ?e w(e)ze Du lt 1 For i 1,,
nets do If pi ? or weight(pi) gt (1??) li
Find path pi with min weight li among
si-ti paths End If xpi xpi 1 For
every v?V(G) and e?E(G) yv yv( 1 ? pi?Ev
/ ?0b(v) ) ze ze( 1 ? pi?Ee / ?0w(e) ) u
u( 1 ? (? ?vpi?Ev ? ?epi?Ee) / D )
End For End For End While Output x scaled by
the number of While iterations
19
Extensions

• Sink delay upper bounds
• (Elmore-Delay)
• Buffer-wire sizing and layer assignment
• Multi-pin nets

20
Experimental Results
21
Experimental Results
22
Experimental Results
23
Conclusions

• First coherent approach to floorplan definition,
  timing and congestion-driven buffered global
  route planning, wire/buffer sizing, layer
  assignment and pin assignment.
• Provably good results by multicommodity flow
  approximation algorithms and randomized rounding.