The 3-D integration technologies: The new challenge of Hybrid Pixels detectors

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The 3-D integration technologies The new
challenge of Hybrid Pixels detectors
2009 CMOS Emerging Technologies Workshop
Research Business Opportunities Ahead

• Patrick Pangaud
• CPPM/IN2P3/CNRS/Université de la Méditerranée,
  Marseille, France

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Centre de Physique des Particules de Marseille,
FRANCE
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Outline

• Hybrid Pixels detectors for High Energy Physics,
  synchrotron facilities, X-rays CT-scanner
• The 3-D integration technologies
• The 3-D Hybrid Pixels detectors
• The new challenge for the post-LHC accelerator

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Hybrid Pixels Detector for LHC/SLHC at
CERN ( Switzerland )
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Hybrid Pixels Detector for particles trackers

• An early 3-D approach!!
• Sensor for particles detection
• Dedicated electronic chip
• AND
• A bump-bonding solder for interconnection

• Sensors (Si, CdTe, GaAs) for ionizing particles
• (e-, photon, gamma, etc ..)
• Electronic pixel readout
• Monolithic device
• Analog detection (low noise, low power)
• Digital readout

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Interest of Hybrid Pixels for X-ray imaging

• Single photon counting (as opposed to charge
  integration)
• Noise suppression
• Energy selection
• Maximum efficiency dose reduction
• High dynamic range flux and luminosity

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Hybrid Pixels detector for HEP (Atlas/LHC
exemple)
And silicon sensor with the same pixel dimension
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Why 3-D ? More than Moore
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3-D integration the market point of view
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3-D methods Vias through silicon
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3-D methods Bonding Choices
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Areas of Interest to HEP

• Major Markets being pursued by Industry for 3D
  integration
• Pixel arrays for imaging
• Memory
• Microprocessors
• FPGAs
• 3-D Pixel arrays with high functionality and
  smaller form factor for particle tracking
• 3-D bonding technology to replace bump bonds in
  hybrid pixel assemblies.

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Understanding the Basic Principles of 3-D
Integration

• Vias
• Via First done at foundry, lowest cost
• Via last after wafers are made, often done by
  third party vendors.
• General movement in industry toward via first
  approach
• Bonding options
• Mechanical bond only, electrical connections
  later
• Oxide to oxide bonding
• Adhesive such as BCB
• Mechanical and electrical connection formed
  together
• CuSn Eutectic
• CuCu Fusion
• Direct Bond Interconnect combination of oxide
  bonding and metal fusion
• Thinning
• Alignment

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3-D integration Via First Approach

• Through silicon Via formation is done either
  before or after CMOS devices (Front End of Line)
  processing

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3-D integration Via Last Approach

• Via last approach occurs after wafer fabrication
  and either before or after wafer bonding

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3-D Hybrid Pixels detector (Atlas/SLHC
exemple)
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Fermilab 3-D Multi-Project Run

• Fermilab has planned a dedicated 3-D multi
  project run using Tezzaron for HEP during 2009
• There are 2 layers of electronics fabricated in
  the Chartered 0.13 um process, using only one set
  of masks. (Useful reticule size 15.5 x 26 mm)
• The wafers are bonded face to face.

ATLAS/SLHC Sub-part
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Tezzaron technology A Closer Look at
Wafer-Level Stacking
Oxide Silicon
Dielectric(SiO2/SiN) Gate Poly STI (Shallow
Trench Isolation)
W (Tungsten contact via) Al (M1 M5) Cu (M6,
Top Metal)
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Tezzaron technology Stack a Second Wafer
Thin
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Tezzaron technology Then, Stack a Third Wafer
3rd wafer 2nd wafer 1st wafer
controller
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Tezzaron technology Finally, Flip, Thin
Pad-Out
1st wafer controller 2nd wafer 3rd
wafer
This is the completed stack!
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Fermilab 3-D Multi-Project Run The Atlas/SLHC
prototype
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Conclusions

• Industry is making rapid progress in developing
  3-D integrated circuits.
• HEP is beginning to respond with new initiatives
  to explore this technology.
• The Hybrid Pixels are good candidates to use 3-D
  integration technology
• A 3-D Hybrid Pixels detector is under study for
  the next version of ATLAS detector for SLHC
• We are very impatient to evaluate it .!!!

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And a special thanks to the ATLAS collaboration,
the FNAL Laboratory and the Tezzaron/Chartered
foundry Thank you for your attention