VLSI Architectures for Iterative Decoders - PowerPoint PPT Presentation

1 / 26
About This Presentation
Title:

VLSI Architectures for Iterative Decoders

Description:

Convolutional/ Low Density Parity Check. Soft-Input-Soft-Output (SISO) Decoders ... LDPC decoding with a regular parity check matrix. Total Number of Edges: 18432 ... – PowerPoint PPT presentation

Number of Views:253
Avg rating:5.0/5.0
Slides: 27
Provided by: yeo9
Category:

less

Transcript and Presenter's Notes

Title: VLSI Architectures for Iterative Decoders


1
  • VLSI Architectures for Iterative Decoders
  • Engling Yeo, Payam Pakzad,
  • Borivoje Nikolic and Venkat Anantharam
  • Department of Electrical Engineering and Computer
    SciencesUniversity of California, Berkeley

2
Outline
  • Objectives
  • Iterative decoder systems
  • Partial Response Channel
  • Convolutional/ Low Density Parity Check
  • Soft-Input-Soft-Output (SISO) Decoders
  • Maximum A-Posteriori Probability Decoder (BCJR)
  • Soft-Output Viterbi Decoder (SOVA)
  • Low Density Parity Check (LDPC) Decoder
  • Computational Complexities

3
Architectural Objectives for Iterative Decoders
  • Speed gt 1Gbps
  • Minimal control logic.
  • Minimized memory requirement by encouraging reuse
    of storage elements.
  • Avoid use of general purpose SRAM memories.

4
ITERATIVE DECODERS
5
Iterative Decoding for Partial Response Channels
? Pseudo Random Interleaver
  • Using a partial response channel as an Inner
    Convolutional Code.
  • Outer code can be either convolutional code or
    LDPC code
  • T. Souvignier, et. al., Turbo Decoding for PR4
    parallel vs. serial concatenation, ICC 1999

6
Unrolled Iterative Decoder
Unrolled decoder employs multiple pipelined SISO
stages to achieve desired throughput rates (gt
1Gbps)
  • G. Masera, et. al., "VLSI Architectures for Turbo
    Codes", IEEE Transactions On VLSI Systems, Vol.
    7, No. 3, Sep. 1999.

7
MAP Decoders (BCJR)
  • L. Bahl, et. al, Optimal Decoding of Linear
    Codes for Minimizing Symbol Error Rate, IEEE
    Trans. Inform. Theory, March 1974.

8
MAP Algorithm
  • Bi-directional trellis path propagation.
  • Forward Propagation ?(k)
  • Backward Propagation ?(k)
  • Probability measure of each state provided by sum
    of forward and backward path metrics.
  • Backward propagation leads to difficulties in
    windowed approaches.

9
Windowed MAP Algorithm
Trellis Position
DISCARD
  • 3-Windowed approach
  • 1 Forward window Width L
  • 2 Backward windows Width 2L

DISCARD
KEEP
DISCARD
KEEP
  • A. Viterbi, An Intuitive Justification and a
    Simplified Implementation of the MAP Decoder for
    Convolutional Codes, IEEE J. on Selected Areas
    in Comm., Vol. 16 No. 2, Feb 1998

KEEP
Time
10
MAP Decoder Block Architecture
11
Timing Diagram for Access to Branch Metric Memory
?(k).
Memory Address
L
3L
2L
L
2L
2L
L
3L
3L
T0
T0
TL
TL
T2L
T2L
Time
T3L
T3L
T4L
T4L
T5L
T5L
T6L
T6L
T7L
T7L
Memory Write Memory Read for a ?-ACSA
Memory Read for 1st b-ACSA window
Memory Read for 2nd b-ACSA window
12
Improved Read Access of Branch Metric Memory
Memory Address
L
2L
3L
T0
  • Partitioning the memory into 3 sections allows
    memory to be implemented with LIFO buffers.
  • Delay forward iteration by 2L steps

TL
T2L
Time
T3L
T4L
Memory Read for ?-ACSA
T5L
Memory Read for 1st b-ACSA
T6L
Memory Read for 2nd b-ACSA
T7L
13
Soft Output Viterbi Decoders (SOVA)
  • Hagenauer, J. Hoeher, P. A Viterbi algorithm
    with soft-decision outputs and its applications.
    GLOBECOM '89

14
SOVA Implementation
  • Provides a measure of confidence by comparing the
    difference in path metric between the most likely
    path (?) and the next most likely path (b).
  • Realize a SOVA decoder by cascading a typical VA
    survival memory unit with a SOVA section.

15
Structure for a 4-State SOVA Implementation
(Register Exchange Method)
Intermediate Path Metric Differences
Reliability Measure Unit
L-TAP
L-TAP
?i
? ? ?
L-TAP
4? ACS
M I N
L-TAP
M I N
? ? ?
?
L-Step Register X-change VA-SMU
di-L-1
di-L
? ? ?
L-TAP
M-Step Register Exchange SOVA SMU
L-TAP
Intermediate decisions
L-TAP
L-TAP
16
Example 4-State Register Exchange SOVA-SMU
Reliability Measure Unit
SOVA Survival Memory Unit
Added XOR gates
Operation of RMU pipeline min Di , Zi-1 ) if
Xi,k 1 Zi Zi-1 otherwise
17
Decoders for Low Density Parity Check Codes (LDPC)
18
LDPC Overview
  • Relationship between each bit and parity check
    can be represented by either parity check matrix
    or the bi-partite graph.
  • LDPC decoding with a regular parity check matrix
  • Total Number of Edges 18432

GALLAGER R. G., IRE Trans. Info. Theory, Vol.
8(1962) p. 21
19
Pipelined Architecture of LDPC Decoder
MEMORY
MEMORY
Bit to Check
Check to Bit
MEMORY
MEMORY
  • Randomness of connectivity in bi-partite graph
    inhibits any kind of memory reuse.
  • Two banks of memory alternating between read and
    write required.
  • Total memory requirement 72k words

20
LDPC Operations
Check-to-Bit
Bit-to-Check
Parallel Tree-Adder Structure
Recursive-Serial Adder Structure
21
Comparison of SISO Decoders
22
Summary of Computational Complexities
23
Summary of Memory Requirements
24
Future
  • Choice of SISO decoder dependent on number of
    variables.
  • SNR of intended environment
  • Targeted BER performance
  • Message wordlength
  • Number of iterations
  • Latencies
  • Timing Recovery
  • Error Propagation
  • Moores Law

25
Conclusion
26
Conclusion
  • Various building blocks for an iterative decoder
    suitable for magnetic recording channels have
    been presented.
  • Proposed timing schedule of MAP decoder allows
    high-speed memory access pattern with minimal
    control logic.
  • SOVA decoder achieved through minimal extensions
    to a Viterbi decoder, and use of high speed
    register exchange.
  • Pipelined LDPC decoder suffers from large memory
    requirements despite low computational costs.
Write a Comment
User Comments (0)
About PowerShow.com