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Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66

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Delivering Success. Modeling 32 V Asymmetric LDMOS Using Aurora ... oscilloscope. VDD. Pulse Gen. Self Heating Effect in HV MOSFET (cont'd) ESSDERC 2007 MUNICH ... – PowerPoint PPT presentation

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Title: Modeling 32 V Asymmetric LDMOS Using Aurora and Hspice Level 66


1
Modeling 32 V Asymmetric LDMOS Using Aurora and
Hspice Level 66
By Alhan Farhanah, Mohd Shahrul Amran, Albert
Victor Kordesch Device Modeling Department,
SILTERRA Malaysia Sdn. Bhd. 2007
2
Outline
  • Aurora and HSPICE Level 66 Background
  • 32V Asymmetric HV MOS Background
  • Modeling Flow for Asymmetric HV MOS
  • Results and Discussion
  • Self Heating Effect in HV MOS
  • Conclusion

3
Aurora and HSPICE Level 66 Background
  • Aurora
  • product of Synopsys Inc for Modeling.
  • Beside HSPICE Level 66, Aurora also offers all
    types of models that normally offered by other
    products.
  • Contends for the modeling and SPICE simulation of
    digital CMOS, analog and RF circuit that operates
    up to 100V.

4
Aurora and HSPICE Level 66 Background (contd)
  • HSPICE Level 66 is a proprietary product of
    Synopsys.
  • HSPICE Level 66 model
  • self heating, forward and reverse mode,
    asymmetric parasitic, and bias dependent RDS-
    based on BSIM4
  • primarily targets for LDMOS (Lateral Double
    Diffused MOSFET) and EDMOS (Extended Drain
    MOSFET) device technologies.

5
32V Asymmetric HV MOS Background (contd)
Structure
6
Modeling Flow For Asymmetric HV MOS
7
Modeling Flow For Asymmetric HV MOS
(contd)Asymmetric Behavior Checking
  • Purpose - check the asymmetric effect of the
    transistor.
  • Measurement - swapping the bias voltage of source
    and drain for each measurement.
  • Compare IdVd curve for forward and reverse mode
    measurement.

8
Modeling Flow For Asymmetric HV MOS (contd)
Asymmetric Behavior Checking
Almost similar ID
Long Channel Device (W/L25u/25u)
forward mode ___ reverse mode
9
Asymmetric Behavior Checking
Significant ID decrease
VGS
forward mode ___ reverse mode
Short Channel Device (W/L25u/4.25u)
10
Modeling Flow For Asymmetric HV MOS (contd)
  • The results showed that shorter length device
    exhibits quite significant Id decrease for
    reverse mode measurement while the long channel
    device exhibits almost similar Id curve for both
    modes of measurement

11
Modeling Flow For Asymmetric HV MOS (contd) DC
Measurement
  • Measurements
  • IdVg_at_low Vdd with different Vb
  • IdVg_at_high Vdd with different Vb
  • IdVd _at_Vb0 with different Vg
  • IdVd _at_high Vb with different Vg
  • Before measuring all the modeling devices, Wide
    Width and small Length transistor with different
    back biases and different temperatures must be
    evaluated first

12
Modeling Flow For Asymmetric HV MOS (contd) CV
Measurement
  • To properly model the effect of asymmetric, the
    modeling structure for CV need to be designed
    with extra structures compare to symmetric
    structure.
  • All the CV modeling structures need to be
    separated into 2 different structures
  • Source design rule
  • Drain design rule.
  • Thus, the CV measurement for asymmetric
    transistor is almost double compare to symmetric
    transistor.

13

Modeling Flow For Asymmetric HV MOS (contd)
Extraction and Optimization
  • Extraction strategy almost similar to BSIM4
  • The preferred mobility model in Level 66
  • MOBMOD0
  • Source and Drain parameters are not equal. e.g
    RSW and RDW, RSWMIN and RDWMIN
  • Both drain side and source side bias dependence
    parameters of LDD resistance can be optimized.

14
Modeling Flow For Asymmetric HV MOS (contd)
Extraction and Optimization
  • There are reverse mode parameters available for
    optimization i.e ETA0I, ETABI, DSUBI
  • Too many of these parameters are not encouraged.
  • Self heating effect can be turned on by setting
    SHMOD1 and RTH0gt0.
  • Strongly advised to set TSHFLAG1 during the
    optimization - internal approximation of self
    heating effect will be used during the
    optimization. Hence, the speed of the
    optimization is significantly improved. In the
    final step, the optimization can be refined by
    setting TSHFLAG0.
  • When self heating is turned on, the temperature
    parameters need to be extracted as much as
    possible before we do extraction for saturation
    region parameters.

15
Modeling Flow For Asymmetric HV MOS (contd)
Extraction and Optimization
  • Disadvantages of Level 66 model
  • Slower model evaluation -includes internal nodes
    (solver need to be invoked for every bias point)
  • There is no reliable way to extract thermal
    capacitance. Thus, we need to develop a method to
    include thermal time constant in our model.

16
Results and Discussion
W/L 25um/25um
Meas ___ Model
17
Results and Discussion (contd)
W/L 25um/4.25um
Meas ___ Model
18
Results and Discussion (contd)
W/L 25um/25um
Meas ___ Model
19
Results and Discussion (contd)
W/L 25um/4.25um
Meas ___ Model
20
Results and Discussion (contd)
Idsat (uA/um)
21
Results and Discussion (contd)
Vth (V)
22
Results and Discussion (contd)
Meas ___ Model
23
Results and Discussion (contd)
Meas ___ Model
24
Results and Discussion (contd)
  • In this paper, IdVg and IdVd curves for 25um/25um
    and 25um/4.25um have been used to demonstrate
    model accuracy.
  • The model also correctly simulates self heating
    effect
  • The model scalability (across W and L) also
    showed a good agreement with measurement data.
    Less than 5.
  • The accuracy of the AC behavior is excellent.
    Less than 1.

25
Self Heating Effect in HV MOSFET
  • If P is moderate(mW), self heating is not severe
    since
  • it reach its thermal equilibrium with its
    environment

26
Experimental setup
Self Heating Effect in HV MOSFET (contd)
VDD
4.7?F
50?
VD
VG
Pulse Gen
oscilloscope
27
Self Heating Effect in HV MOSFET (contd)
VG
VD
Dynamic response of HV NMOS to typical gate pulse
28
Self Heating Effect in HV MOSFET (contd) RTH
extraction
  • RTH will be extracted from Aurora by fitting the
    data for W25um and different L.
  • set SHMOD1 and RTH0gt0.
  • This is to ensure that the RTH can be scaled with
    L.

29
Transient drain-current characteristics of HV NMOS
Due to SHE
30
Time constant for self heating of HV NMOS
31
Self Heating Effect in HV MOSFET
(contd)Extracted time constant and CTH
  • Time constant is extracted from
  • y 2.3011e-0.0546x
  • where thermal time constant, RTH CTH 1/0.0546
  • 18.32
    us
  • From Aurora extraction RTH 6.85E-03 mºC/W
  • Hence the extracted thermal capacitance
  • CTH 18.32us/RTH
  • 2.67E-03 (Wsec)/ mºC

32
Conclusion
  • Modeling strategies for 32V asymmetric HV MOSFET
    using Aurora and HSPICE level 66 has been
    presented
  • Model shows
  • Excellent DC IV results for entire DC bias range
  • Excellent behavior of junction capacitances
  • Model scalability (across W and L) also showed
    good agreement with measurement data. Less than
    5
  • Correctly simulate SHE
  • Extraction of Thermal resistance and capacitance
    by Pulsed gate measurement

33
Thank You
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