Teaching Computer Design Using Virtual Prototyping - PowerPoint PPT Presentation

Loading...

PPT – Teaching Computer Design Using Virtual Prototyping PowerPoint presentation | free to download - id: 114a27-NmJlM



Loading


The Adobe Flash plugin is needed to view this content

Get the plugin now

View by Category
About This Presentation
Title:

Teaching Computer Design Using Virtual Prototyping

Description:

Oscilloscopes, - Logic programmers that they use to build. and debug their designs. ... Use the logic analyzer and oscilloscope to observe operation and measure timing ... – PowerPoint PPT presentation

Number of Views:55
Avg rating:3.0/5.0
Slides: 29
Provided by: admi1183
Learn more at: http://www.cpe.ku.ac.th
Category:

less

Write a Comment
User Comments (0)
Transcript and Presenter's Notes

Title: Teaching Computer Design Using Virtual Prototyping


1
Teaching Computer Design Using Virtual Prototyping
Presented by U.Hatthasin
  • Ronald D. Williams, Senior Member, IEEE, Robert
    H. Klenke, Senior Member, IEEE, and
  • James H. Aylor, Fellow, IEEE

IEEE TRANSACTIONS ON EDUCATION, VOL. 46, NO. 2,
MAY 2003
2
Overview
I. INTRODUCTION
II. ECE 435 COMPUTER ORGANIZATION AND
DESIGN
III. ECE 436 ADVANCED DIGITAL DESIGN
IV. AN EXAMPLE FINAL PROJECT
V. CONCLUSION
DISCUSSION
3
I. INTRODUCTION
  • The rapid increase in complexity and size of
    digital systems has reduced the effectiveness of
    old design methodologies based on physical
    prototyping.
  • This virtual prototyping design methodology often
    permits the first physical prototype to be a
    manufacturable product.
  • The Computer Engineering group of the University
    of Virginia has developed and implemented a
    sequence of two senior- level courses that fully
    embrace the concept of virtual prototyping.
  • ECE435 Computer Organization and Design
  • ECE436 Advanced Digital Design

4
I. INTRODUCTION (cont.)
  • To provide the students with a range of practical
    prototyping experiences
  • The first design pass uses only design capture
    and simulation and serves to convey the basics of
    design and the tools.
  • The second pass involves design refinement and
    synthesis, and it clarifies the function of
    design iteration and tradeoff analysis.
  • The major effort to design a complete digital
    processor is effectively completed twice

- Once as an individual effort during the first
course
- Again as a team effort during the second
course.
5
II. ECE 435 COMPUTER ORGANIZATION AND DESIGN
  • A. ECE435 Lectures
  • B. ECE 435 Labs
  • C. Methodology
  • D. Tools
  • E. Functional Testing
  • F. Results

6
A. ECE 435 Lectures
  • Teach the students the concepts of computer
    design at the register transfer level.
  • Elements are presented along with...

- Computer design techniques and tools,
- Simulation-based design,
- The Hardware Description Language (HDL).
  • Once the students understand the basics of
    hardware description, the lectures shift to
    computer design and organization.

7
B. ECE 435 Labs
  • Most of the labs demonstrate how to write,
    compile, and simulate VHDL code.
  • The major focus of these labs is the design of a
    data path and control unit that can implement the
    instruction set architecture (ISA) of a small
    8-bit computer called the 35VEE8.
  • The instruction set for the 35VEE8 was given to
    the students at the beginning of the semester in
    the form of a programmers reference manual so
    that they knew the functionality objectives from
    the start of their design.

8
B. ECE 435 Labs (cont.)
  • The laboratory assignments

1) Design, describe in VHDL, and simulate a 1-bit
arithmetic and logic unit (ALU). Cascaded
together, these form an ALU of arbitrary bit
width.
2) Using the 1-bit ALU from the previous
laboratory exercise, compose and simulate an
8-bit ALU.
3) Design, describe in VHDL, and simulate an
8-bit two-to-one multiplexor and an 8-bit
transparent latch.
9
B. ECE 435 Labs (cont.)
4) Design a data path on paper that is capable of
performing all the specifications for the
35VEE8.
5) Implement and simulate the data path design.
6) Design and simulate a control.
7) Connect the data path and the control unit
together.
8) Run a sample program and determine the maximum
clock frequency, number of clock cycles, and the
average execution time per instruction.
10
C. ECE 435 Methodology
  • The design methodology is a mixture of top down
    and bottom up.

top-down manner
- Create a library of register-transfer-level
components.
  • Return to the top-level specification, the
    programmers
  • reference manual,
  • Proceed to design the data path and control unit
    for
  • processor

11
D. ECE 435 Tools
  • Design Architect is used for basic VHDL
    development work.
  • Graphical system composition produces VHDL as its
    output for simulation.
  • Mentor Graphics QuickHDL is used on UNIX
    workstations.

12
E. ECE 435 Functional Testing
  • The students must provide simulation results.
  • Individual blocks have been verified, placed
    together into larger units, and simulated.
  • Most students simulate their data path
    independently from the control unit to make sure
    that each performs at least a portion of the
    instructions correctly.
  • Next the data path is integrated with the control
    unit, and individual instruction execution is
    tested.
  • Timing analysis is also required for some of the
    labs.

13
F. ECE 435 Results
  • In each year that the course has been offered,
    approximately 90 of the class has produced a
    working processor at the completion of the class.

14
III. ECE 436 ADVANCED DIGITAL DESIGN
  • A. ECE436 Lectures
  • B. ECE 436 Labs
  • C. ECE 436 Project
  • D. Methodology
  • E. Tools
  • F. Construction
  • G. Functional Testing
  • H. Results

15
A. ECE436 Lectures
  • The objective of this second course is to
    implement designs in hardware.
  • Logic decomposition gt to partition the designs
    in FPGA or PLD architectures
  • The differences among logic families and the
    advantages and disadvantages
  • Discussed and compared to fault models,
    generation and reduction of fault tables, fault
    simulation algorithms.
  • Testability techniques to assist with debugging
  • Different levels of design including register
    transfer, logic, algorithm and behavioral, and
    system level.

16
B. ECE 436 Labs
  • The laboratory assignments was designed to
    familiarize the students with the use of the test
    equipment such as..

- Logic analyzers,
- Oscilloscopes,
- Logic programmers that they use to build
and debug their designs.
  • The laboratory assignments

1) Using Actel macros, design an arithmetic logic
unit (ALU) for the 35VEE8 that can be
implemented in an Actel FPGA. Use the ALU and
models of discrete components to implement a
16-bit adder.
17
B. ECE 436 Labs (cont.)
2) Write a synthesizable behavioral VHDL
description of the 35VEE8 ALU. Use the Leonardo
synthesis tool to develop a gate level
implementation using Actel macros. Incorporate
this ALU into the 16-bit adder datapath developed
in the previous assignment and test.
3) Write a synthesizable behavioral VHDL
description of the memory controller state
machine to be used in the 35VEE8 system.
Synthesize the gate level implementation using
Autologic. Implement that design in a 22V10
programmable array logic (PAL) using the PLDSII
tool.
  • 4) Use the logic analyzer and oscilloscope to
    observe operation and measure timing delays for a
    test circuit implemented using an Actel FPGA and
    22V10 PAL.

18
C. ECE 436 Project
  • The first deadline

- The critical design review .
- Presenting overall design methodology and
any risk areas
- The course instructors attempt to ascertain
from the presentation that the groups
design is technically correct and that
they are on schedule to complete the
design.
  • The second deadline

- Final demonstration using a benchmark program.
  • - Timed to determine the performance of the
    design.

- Final written report for the completion of the
project.
19
D. ECE 436 Methodology
  • top-down manner

- Project is intended to provide practical
experience in implementation techniques and
teamwork.
- Implementing components in the Actel PFGA
parts.
  • bottom-up manner

- The components are wired together to implement
the 35VEE8 computer.
- The students implemented their design,
completed and verified via extensive simulation.
- Implemented by wire wrapping the programmed
chips onto a prototyping board.
20
E. ECE 436 Tools
  • The same CAD tools in ECE435 are used

- Schematic capture gt registers, to lay out
datapaths
  • - VHDL and synthesis gt state machines, blocks
    of
  • combinational logic such as ALUs and
    decoders

- Functional simulation accomplished by..
1. Timing simulations of the entire design
2. Placement and routing of the complete FPGA
21
F. ECE 436 Construction
22
G. ECE 436 Functional Testing
  • Performed at almost every step through the
    prototyping process.
  • Broad stage without timing values.
  • Functional simulations with a fast
    edit-simulate-check cycle.
  • Routed both gate delays and routing delays
  • Tested using standard test bench instruments.

23
H. ECE 436 Results
  • Over 80 of the groups to get the prototypes to
    function correctly for a significant portion of
    the instruction set.
  • Only one group has failed to complete a virtual
    prototype.
  • Most of the groups have experienced wiring errors
    and even some microcode mistakes, but all of
    these problems were resolvedin a minimum of time
    and without change to the physical design.
  • The average time from the beginning of
    construction is about four days.

24
IV. AN EXAMPLE FINAL PROJECT
25
IV. AN EXAMPLE FINAL PROJECT
26
V. CONCLUSION
  • The two-course sequence based on virtual
    prototyping was considered to be a success.
  • Student opinion of these courses was very good
    with many students commenting on the great
    satisfaction that they enjoyed when they were
    able to run a program on a computer of their own
    construction.
  • A few commented that they gained a much greater
    understanding of computer architecture
    fundamentals through this extended design effort.
  • The education of students in simulation-based
    design is becoming increasingly important.

27
DISCUSSION
  • The limitation on the number of available Actel
    FPGAs and the difficulty in making design changes
    in a wire wrapped board demands extensive
    simulation to remove functional bugs before
    construction
  • Reducing design cost and time-to-market while
    allowing a greater exploration of the design
    space makes it required technology for remaining
    competitive in todays digital system market.

28
The End.
About PowerShow.com