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Incircuit verifisering og validering av FPGA systemer Bjrn Sveum Nortelco Electronics AS

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MSOs offer more channels and wider logic triggering than oscilloscopes ... MSO4000 Mixed-Signal Oscilloscope, or TLA Series Logic Analyzer ( v4.3) Test. Equipment ... – PowerPoint PPT presentation

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Title: Incircuit verifisering og validering av FPGA systemer Bjrn Sveum Nortelco Electronics AS


1
In-circuit verifisering og validering av FPGA
systemer Bjørn SveumNortelco Electronics AS
2
Examples of FPGAs
3
Potential Problems
  • Functional definition errors
  • At the FPGA or system level
  • Functional system interaction problems
  • System-level timing issues
  • Asynchronous events
  • Real-world interactions, especially at speed
  • Difficult to simulate timing violations
  • Signal fidelity between ICs
  • Noise, cross-talk, reflections, loading, EMI
  • Interconnect reliability issues
  • Solder joints, connectors
  • Power supply issues
  • Transients and load variations
  • High power dissipation
  • Undiscovered FPGA design errorsdue to incomplete
    simulation
  • Too complex to provide 100 code coverage
  • Too time-consuming to implement and run

4
FPGA Debug Challenges
  • Design verification has become a critical
    bottleneck
  • Increased design size and complexity
  • Limited access to internal signals
  • Time-to-market constraints reduce debugging time
  • Debugging can take gt50 of design cycle time
  • Simply looking at the external pins is inadequate
  • Adding debug circuitry to FPGA affects the design
  • Consumes valuable chip real estate
  • Requires additional time
  • May affect the designs timing performance
  • Access usually uses up scarce pins on the chip
  • Probing many signals on the board may be difficult

5
Debugging FPGA Designs
  • Challenge
  • How to get visibility into FPGAs that are getting
    bigger and more complex?
  • Review 2 Basic Methodologies
  • advantages and disadvantages of each
  • Conclusions
  • Is there a best methodology?

6
Simulation
  • Simulation can help reduce debug time by catching
    obvious errors, but simulation can not catch all
    problems!
  • Can not simulate asynchronous events
  • Hard to simulate real-world interactions,
    especially at speed
  • Difficult to simulate timing violations
  • 100 Code Coverage is Difficult
  • Simulation runs are slow

PCI PCIBridge
33 MHz PCI Bus
FPGA
22 MHz System Bus
System Hardware
7
FPGA Design Process
  • Design Phase Tasks
  • Design Entry
  • Design Implementation
  • Simulation
  • Debug and Verification Phase
  • Validate Design
  • Correct any Bugs found
  • Debug and Verification Methods
  • Simulation
  • In-Circuit Verification

8
Overview of In-Circuit FPGA Debug MethodsBasic
Approaches
  • Embedded Instruments
  • Embed a logic analyzer/bus analyzer into your
    design
  • Logic analyzer functionality is inserted in
    design
  • SignalTap II (Altera)
  • ChipScope ILA (Xilinx)
  • External Instrument
  • 11 Signal/Pin
  • Modify RTL as needed
  • Take advantage of the programmability of the FPGA
    to route internal signals to a small number of
    pins
  • Use FGPA tools to add Probes to your design
  • Adds a green wire to your FPGA
  • SignalProbe (Altera)
  • PROBE (Xilinx)
  • N1 Signal/Pin
  • Insert a test mux
  • Allows more visibility than Modify RTL method
  • Instrument-controlled test mux
  • Creates instrument awareness and control of
    inserted test mux

9
Embedded Logic AnalyzerSignalTap II / ChipScope
ILA / CLAM
  • FPGA vendors offer logic analyzer cores
  • Inserted in design and contain triggering and
    trace storage resources
  • Uses FPGA resources
  • Core is accessed via JTAG
  • Data displayed in FPGA vendors viewer application
  • Advantages
  • Fewer pins required. Uses JTAG pins
  • Simple probing
  • Just hook up JTAG cable
  • Embedded logic analyzer cores are relatively
    inexpensive
  • Disadvantages
  • Size of core limits use to large FPGAs
  • Designers have to give up internal memory for
    trace storage
  • Limited memory depth
  • Data can be captured in state mode only and at a
    limited speed
  • Limited to fastest clock in FPGA
  • Cant correlate (see) FPGA trace data with other
    system traces

10
External Test EquipmentOscilloscopes
  • Inserts custom debug code in design
  • Leverages the programmability of FPGA
  • Can route copies of internal signals of
    interestto output pins for viewing
  • Can implement complex triggering internally
  • User interface is familiar and frequently used

FPGA
Debugcode
DPO/DSA SeriesOscilloscopes
  • Advantages
  • Lowest (capital) cost technique
  • May use few FPGA logic resources
  • Uses no FPGA memory
  • Can correlate FPGA signals to other analog or
    digital signals system
  • Disadvantages
  • Debug code must be redesigned and recompiled for
    each experiment.
  • Consumes valuable FPGA gates and pins
  • Very limited visibility of complex designs
  • Limited by pins and scope channels
  • Inefficient technique for complex designs

11
External Test EquipmentMixed-Signal Oscilloscopes
  • Inserts custom debug code in design
  • Leverages the programmability of FPGA
  • Can route copies of internal signals of
    interestto output pins for viewing
  • Can implement complex triggering internally
  • MSO may reduce this need

FPGA
Debugcode
MSO SeriesMixed-SignalOscilloscopes
  • Advantages
  • MSOs offer more channels and wider logic
    triggering than oscilloscopes
  • MSOs offer parallel bus and event table displays
    of the digital signals
  • May use few FPGA logic resources
  • Uses no FPGA memory
  • Can correlate FPGA signals to other analog or
    digital signals system
  • Disadvantages
  • Debug code must be redesigned and recompiled for
    each experiment.
  • Consumes valuable FPGA gates and pins
  • Visibility of complex designs somewhat limited by
    pins
  • Have to manually update signal names and channel
    assignments on MSO

12
External Logic AnalyzerModify RTL source as
needed
  • Take advantage of the programmability of the FPGA
    to route internal signals to a small number of
    pins
  • 11 Relationship of internal signals to FPGA pins
  • Use external logic analyzer to capture data
  • Advantages
  • Use few, if any, FPGA logic resources
  • Uses no FPGA memory
  • Data can be captured in state mode and in timing
    mode
  • Can correlate (see) FPGA signals to other system
    signals
  • Disadvantages
  • Requires more pins on FPGA
  • Moving probe points can take a recompile of the
    design
  • Uses time and changes timing of design
  • Have to manually update signal names on logic
    analyzer

13
External Logic AnalyzerInsert a test mux
  • Increased visibility of internal signals
  • N1 relationship of internal signals to pins
  • Use external logic analyzer to capture data
  • Advantages
  • Use few FPGA logic resources
  • Uses no FPGA memory
  • Data can be captured in state mode and in timing
    mode
  • Can correlate FPGA signals to other system
    signals
  • Eliminates need to recompile design
  • Disadvantages
  • Requires more pins on FPGA
  • Requires a test mux
  • Requires a way to control test mux
  • Still have to manually update signal names on
    logic analyzer

14
Use FGPA tools to add Probes to your
designGreen Wire
  • FPGA vendors offer ability to add green wire to
    design
  • Does not require modification to RTL
  • 11 Relationship of internal signals to FPGA pins
  • Use external logic analyzer to capture data
  • Advantages
  • No modification of RTL required
  • No need to recompile design
  • Uses no FPGA memory
  • Data can be captured in state mode and in timing
    mode
  • Can correlate FPGA signals to other system
    signals
  • Reduces need to recompile design
  • Disadvantages
  • Requires more pins on FPGA
  • Requires a test mux
  • Requires a way to control test mux
  • Still have to manually update signal names on
    logic analyzer

15
Instrument-controlled test mux
  • Closed-loop system between FPGA and test
    equipment
  • Test equipment is aware of the design
  • Increased visibility of internal signals
  • N1 relationship of internal signals to pins
  • Use external logic analyzer to capture data
  • Disadvantages
  • Requires more pins on FPGA
  • External instrument vendor specific
  • Advantages
  • Uses no FPGA memory
  • Test Mux designed and tested by 3rd party
  • Data can be captured in state mode and in timing
    mode
  • Can correlate FPGA signals to other system
    signals
  • Eliminates recompiles

16
Picking the Right FPGA Debug Methodology
17
FPGA DebugSummary
  • Is there a best methodology for all designs?
  • NO!
  • But Choosing the right FPGA debug methodology
    for your design can reduce debug and validation
    time.
  • Make the choice early in the design phase.
  • Are you pin-constrained or FPGA-resource
    constrained?
  • Choice of methodology impacts the design of the
    board
  • How to connect to external instrument?
  • FPGA Pin useage
  • Embedded logic analyzers and external logic
    analyzers each have trade-offs.
  • Pins vs. Resources
  • Ability to correlate FPGA signals to board-level
    signals
  • Power of instrument
  • Memory, triggering, resolution

18
Improving the External Test Equipment Method with
FPGAView
  • A Tektronix and First Silicon Solutions (FS2)
    collaboration

Supports all Tektronix TLA Series Logic
Analyzers and MSO Series Mixed-Signal
Oscilloscopes
Supports complete range of Xilinx and Altera FPGAs
FPGAView from First Silicon Solutions
19
Real-Time Logic Debug Solution for FPGAsOverview
  • FPGAView
  • Supports Xilinx and Altera FPGA devices
  • Software package developed by First Silicon
    Solutions (www.fs2.com)
  • Runs on Windows 2000 andWindows XP machines


  • Logic Analyzer
  • Mixed-Signal Oscilloscope

FPGAView Software
FPGAView Software
PC Board
PC Board
FPGA
P6516Probe
FPGA
TekVISA
TLA Probe
Test Mux
Test Mux
JTAG
USB
JTAG
USB
JTAG Cable
JTAG Cable
20
Using FPGAView4 Easy Steps
Create the Interface Block
Configure FPGAView for your debug environment
Map FPGA Pins to Logic Analyzer or MSO
Make Your Measurement
  • Step 1 - Create the Logic Analyzer or MSO
    Interface Block
  • Step 2 - Configure FPGAView for your debug
    environment
  • Step 3 - Map FPGA Pins to Logic Analyzer or MSO
  • Step 4 - Make Your Measurement

21
Using FPGAViewStep 1 Create and Insert the
Interface Block
  • Altera
  • Use Altera Quartus II Logic Analyzer Interface
    Editor to define and insert Logic Analyzer
    Interface
  • Available in all editions of Quartus II,
    including free Web Edition
  • Xilinx
  • Use FS2 On-Chip Instrumentation Generator
    (OCIGEN) to define and insert a test core into
    your design

22
Using FPGAViewStep 1 Create and Insert the
Interface Block
  • Altera
  • Define Test Core Parameters using Quartus II
    Logic Analyzer Interface Editor

Specify number ofdebug pins
Specify Number of Banks
Specify Mode
Specify Clock(if using State Mode)
23
Using FPGAViewStep 1 Create and Insert the
Interface Block
  • Altera
  • Use Node Finder to select signals and assign to
    banks

24
Using FPGAViewStep 1 Create and Insert the
Interface Block
  • Xilinx
  • Define Test Core Parameters using FS2 On-Chip
    Instrumentation Generator (OCI Gen)
  • Can optionally insertGeneral-Purpose IO
    registers thatcan be set/read via JTAG interface
  • Core is inserted in your HDL code

Specify Mode
Specify Number of Banks
Specify number ofdebug pins
25
Using FPGAViewStep 1 Create and Insert the
Interface Block
  • Xilinx
  • Select signals to probe

26
Using FPGAViewStep 2 Configure FPGAView
Communication
Specify JTAG Interface
Specify TLA Interface
27
Using FPGAViewStep 3 Map FPGA Pins to Logic
Analyzer or MSO
  • Use FPGAView to connect FPGA pins to external
    test equipment
  • Enables automatic channel name updating
  • Drag Drop operation
  • Supports multiple Test Cores / FPGAs

28
Using FPGAViewStep 4 Make Your Measurement
  • Use Bank pull-down list to select Bank to measure
  • After selection, FPGAView sets up test core via
    JTAG
  • Programs the Logic Analyzer or MSO with the
    proper signal names
  • Makes it easy to interpret measurement results
  • Easily switch internal probe points by selecting
    a different Bank
  • No need to recompile your design
  • Correlate FPGA signals with other signals in your
    system

29
ExampleUsing FPGAView to Debug a State Machine
  • Select the State Bank using FPGAView
  • Probes the current state of the state variables
    as well as key control signals related to state
    machine

30
ExampleUsing FPGAView to Debug a State Machine
  • Set the TLA Logic Analyzerto trigger on
    suspected error
  • Multiple load pulses

Unexpected State Machine transitions
31
Summary
  • Reduce Debug and Validation Time
  • Choosing the right FPGA debug methodology can
    reduce debug and validation time
  • Understand the Trade-offs
  • Embedded logic analyzers and external test
    equipment each have their own advantages and
    disadvantages
  • FPGAView Eliminates Most of the External Test
    Equipment Trade-offs
  • Enables real-time debugging of Xilinx and Altera
    FPGAs
  • For RD engineers designing with Xilinx and
    Altera FPGAs
  • Allows design teams to view the internal
    operation of their Xilinx or Altera FPGA design
  • Allows correlation of these signals with other
    board signals
  • Increases productivity and cuts debugging time
  • Change internal probe points in instant no need
    to recompile your design
  • Monitor multiple internal signals per debug pin
  • Easier to use and less intrusive than other debug
    methodologies!
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