Project Review Meeting

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MODERN ENIAC WP2 Meeting

• WP2 Tasks review summary
• Catania, 2010 Nov. 09-10

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Contents

• WP2
• Task 2.1 to 2.5 summary
• Matrix, Gantt chart, relation with other Wps
• Action points from meeting

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WP2 Relationship among work packages
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WP2 Objectives

• Objectives
• Provide a chain of TCAD simulations tools which
  enable simulation of the impact of process
  variations and reliability on device level,
  including compact models and mixed mode
  device/circuit simulation
• Assess the impact of process and device
  variations for relevant technologies, mainstream
  planar bulk CMOS down to 45/32nm, new device
  architectures on bulk on SOI suitable for 22nm,
  NVM technologies, and non-silicon technologies
• Compare simulation results with hardware and
  calibrate them on hardware to verify PV
  methodology and to foster physical understanding
  of major sources of PV in above technologies

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WP2 Key Figures

• 5 Tasks/18 deliverables (reports)
• Process (2) device (6) simulation
• Electrical characterization (4) Reliability(3)
• Compact modeling (3)
• Covering both Tools/Methodology improvements and
  Application results
• Wide spectrum of technologies devices
  applications
• 45nm planar Mosfet
• 32nm planar Mosfet, FinFet
• 22nm FD SOI Mosfet
• State-of-art NVM
• Discrete Power Device, SiC, GaN/AlGaN
• HV CMOS
• TOTAL EFFORT 638.6 PM 53.22 PY
• Reference MODERN Rev2.1.7 project description

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WP2 meetingDomain overview per task and partner
Technologies Process simulation Device simulation Electrical Charact. Reliability Compact Modeling
Task 2.1 2.2 2.3 2.4 2.5
HVMOS AMS TUW AMS TUW AMS TUW
Planar CMOS 65nm UNCA
45nm UNGL POLI SNPS (STF2) IMEP STF2 UNGL UNGL POLI STF2 NXP
32nm UNGL POLI (STF2) IMEP STF2 UNGL
NVM 41nm UNET NMX SNPS UNET NMX UNET (NMX) UNET NMX
FDSOI IMEP (STF2) LETI IMEP LETI
Finfets, MUG, GAA STF2 NXP IMEP
SiC Power MOS STI STI STI
AlGaN-GaN HEMT STI STI STI

• PV aware tools and methods are of common
  interest they are developped and applied to a
  wide spectrum of technologies (Project book rev2
  v2.4.1).
• Significant communalities of technology targets,
  except different ones for Process and Device
  simulation.
• (not funded)

MODERN General Meetings Catania, Nov. 9 10, 2010
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WP2 Task Definition and Contributors
WP2 Process/Device to Compact Modeling Contributors
T2.1 PV aware process simulation ST-I, AMS, TUW
T2.2 PV aware device simulation UNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS
T2.3 Electrical characterization of PV, software (TCAD) / hardware comparison calibration NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I
T2.4 Correlation between PV and reliability, reliability modeling AMS, IMEP, UNET, TUW, UNCA, UNGL
T2.5 PV aware compact modeling UNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNG
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WP2 Task Leaders
WP2 STF2 Andre.Juge_at_st.com
T2.1 ST-I valeria.cinnera_at_st.com
T2.2 UNGL a.asenov_at_elec.gla.ac.uk
T2.3 NXP hans.tuinhout_at_nxp.com
T2.4 AMS Jong-mun.park_at_austriamicrosystems.com 
T2.5 UNET paolo.pavan_at_unimore.it
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Contents

• WP2 introduction
• Task 2.1 to 2.5 summary
• Matrix, Gantt chart, relation with other Wps
• Action points from meeting

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MODERN General MeetingTask 2.1 summary

• Catania, Nov. 9-10 2010

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Process simulation T2.1 Deliverables
Ref Deliverable/ Contributors Due date
D2.1.1 First process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) M15 Done
D2.1.2 Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) M27
Task Leader valeria.cinnera_at_st.com
14/05/2015
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ST-I WP2 Activity
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PCM approach

• Synopsys platform
• Sentaurus and PCM Studio
• Simulation of Power-Mos semi cell with the
  nominal values of the process input parameters

• Parameter screening to identify the process
  parameters that
• have an important impact on target electrical
  parameters.
• Parameterized simulation setup (DOE) generating
  several simulation runs.
• Device simulations of breakdown and I-V
  characteristic for each experiment.
• Extraction of RSM model of device
  characteristics as function of process parameters
  using PCM Studio.

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Process Variation at AMS - TUW

• Process Flow

Parameters
Correlation
Interface between commercial Synopsys Process
Simulator and Minimos Device Simulator
Sentaurus Work Bench
Parameter Extraction
Minimos
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WP2 T2.1 action items

• Task 2.1 Process simulation
• D2.1.2 (M27)   Enhanced process simulation
  including treatment of PV for Discrete Power
  Device, HV-CMOS, SiC, GaN/AlGaN technologies,
  interfaced to commercial TCAD tools (ST-I, AMS,
  TUW) 
• AI (STI, AMS, M27) HVMOS and AsGaN-SiC device
  sensitivity analysis to Process variations to be
  validated on HW data available from D2.3.2

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MODERN General MeetingTask 2.2 summary

• Catania, Nov. 9-10 2010

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Device Simulation T2.2 Deliverables
Ref Deliverable/ Contributors Due date
D2.2.1 Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools (UNGL) M6
D2.2.2 Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies, and Discrete Power Device,SiC, GaN/AlGaN technologies. Prototype implementation of the treatment of individual dopants and traps in the device modeling tools (UNGL, UNET, NXP, ST-I, SNPS) M12
D2.2.3 Device simulation analysis of dominant variability sources in state of-the-art Non-Volatile-Memory technologies (UNET, UNGL, NMX, SNPS) M18
D2.2.4 Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET). Efficient compact model extraction procedures for modeling process variations and device fluctuations (NXP, UNET, POLI) M24
D2.2.5 Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations (UNET) TCAD based assessment of PV effects of potential 22nm device architectures (UNGL) M27
D2.2.6 Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2) M36
Task Leader a.asenov_at_elec.gla.ac.uk
14/05/2015
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T2.2.2 Overview
VD1.0V
VD50mV
VD50mV
VD1.0V
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T2.2.2 Overview
(UNET-Università di Udine)
(Synopsys)
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T2.2.2 Overview
(UNET-Università di Bologna)
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T2.2.3 Overview
ltVTgt V sVT mV
RDD (Glasgow) 1.02 141
RDD (Numonyx) 1.15 146
RDF (Synopsys) 1.025 137
RDD
LER
LWR
OTF
ITC
PSG
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T2.2.3 Overview
Flat AA FG
Rounded AA FG
ltVTgt V sVT mV
RDD (Glasgow) 1.02 141
RDD (Numonyx) 1.15 146
RDDRounded (Numonyx) 1.19 161
ltVTgt V sVT mV Calc. sVT mV
Uniform 1.04 - -
All Sources 1.32 169 166.3
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T2.2 action items

• Task 2.2 Device simulation
• D2.2.4 (M24)  Forecast of the magnitude of
  statistical variability in 32nm planar bulk CMOS
  devices via device simulation (UNGL, IMEP, UNET)
• AI (STF2, Nov 2010) to provide TCAD decks.
  5-way NDA between UNGL-UNET-SNPS-POLI-ST applies.
• D2.2.5 (M27)  TCAD based assessment of PV
  effects of potential 22nm device architectures
  (UNGL)
• gt AI (WP leader, Nov 2010) contact LETI on
  demonstrator devices (FDSOI, Finfets?,) and
  associated templates. Backup template devices
  already available at UNGL. Need decision latest
  Feb 2011.
• D2.2.6 (M36)  Sensitivity analysis of Non
  Volatile Memory device performance as a function
  of individual trap position (NMX,UNET) . Toolbox
  (methodologies, models, tools) to make dominant
  variability effects accessible to industrial
  usage of TCAD. Outlook to 16nm device
  architecture robustness using MASTAR (UNGL,
  STF2)
• gt AI(T2.2 Leader) Contact SNPS if they intend
  to contribute to toolbox

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MODERN General MeetingTask 2.3 summary

• Catania, Nov. 9-10 2010

25
Electrical Characterization T2.3 Deliverables
Ref Deliverable/ Contributors Due date
D2.3.1 Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (STF2, IMEP, UNET, NXP) Experimental characterization of Non-Volatile- Memory devices in the presence of PV (NMX, UNET) Parametric mismatch fluctuation effects in 32 nm FinFETs, first PV results on 22nm FDSOI MOSFETS (LETI, NXP) M12
D2.3.2 Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (ST-I) Report on 1/f noise dispersion behavior in 45nm bulk CMOS (NXP) M18
D2.3.3 Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware (STF2, NXP, UNET, AMS) Sources for PV in new device architectures, suitable for 22nm CMOS major deltas in comparison to standard planar bulk CMOS (IMEP, NXP, LETI) M30
D2.3.4 Report on high-level models, both analytical and graphical , for PV of Non-Volatile-Memory devices (NMX) Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS (NXP) M36
Task Leader hans.tuinhout_at_nxp.com
Project Review Meeting Crolles, June 22, 2009
14/05/2015
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Task T2.3 D2.3.1 Characterization of the
influence of variability sources in planar bulk
CMOS devices down to 45nm (ST, IMEP, UNGL)
W (µm) L (µm)
0.12 5
1 0.04
5 0.04
0.15 0.04
0.15 1
0.12 1
1 0.05
1 0.08
0.12 0.05
0.12 0.2

• Example of 45nm Nmos with pocket implants
• Conventional DOE and electrical characterization
  technique
• Geometry scaling on transistor area impacted by
  Lateral doping gradient
• Compact analytical model developed with 3
  channel regions wi/wo pockets explains
  qualitative trend of Lscaling for VT mismatch
• UNGL 3D simulation (D2.2.2) in line with
  experiments

MODERN 1st Year Review June 30, 2010
MODERN 1st Year Review June 22, 2010
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Task T2.3 D2.3.1 Experimental characterization
of NVM devices (41nm, xGbits )in the presence of
PV (NMX)

• Neutral device scaling
• Local random variations for W,L, Oxide, Interpoly
  dielectric, RDD fluctuations (top)
• Local systematic Cell to cell interference
  (bottom)

• After programming
• Local random
• Local systematic VT Shift induced by neighbouring
  cells (top), or string series resistances
  (bottom)

MODERN 1st Year Review June 30, 2010
MODERN 1st Year Review June 22, 2010
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Task T2.3 D2.3.1 First PV results on 22nm FDSOI
MOSFETS (Leti, NXP)
VT mismatch (_at_ 1V Vd) for FDSOI nFETs and pFETs.
High-k/metal gate stack. STI isolation. TSi6nm,
Lmin30nm, Wmin80nm
VT mismatch for UT2B vs thick BOX MOSFETs.
High-k/metal gate stack. STI isolation. TSi8nm.

• Record matching performance for FDSOI (top)
• VT matching not degraded by UTBOX vs Thick box
  substrates (bottom)

MODERN 1st Year Review June 30, 2010
MODERN 1st Year Review June 22, 2010
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Task T2.3 D2.3.1 Parametric mismatch fluctuation
effects in 32 nm SOI FinFETs (NXP, LETI)
Mismatch signature analysis on FinFET population.
WFin10 nm, Lg100 nm a collection of 96
(VDS1.2 V) transfer curves for transistor 1
(ID1) of each pair. b ?ID/ID vs. VGS for all
pairs of the population (?ID/ID 200 x
(ID1-ID2)/(ID1ID2) ). c mismatch signature
s_?ID/ID (red triangles) and mismatch
auto-correlation (black Xs) vs. VGS.
a Drain access resistance improvement from 700
to 280 Oµm . ? vs. ß slope corresponds to RSD.
b VT mismatch fluctuations vs. area. A?VT
increases from 1.9 mVµm (solid line) to 2.4 mVµm
(dashed line) with 1018 channel doping

• Powerful Mismatch signature analysis concept
  demonstrated
• A?VT down to 2 mVµm range demonstrated

MODERN 1st Year Review June 30, 2010
MODERN 1st Year Review June 22, 2010
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T2.3 action items

• Task 2.3 Characterization and simulation
  verification
• D2.3.2 (M18)/D2.3.4 (M36)  1/f noise
  dispersion
• gt AI (WP leader) Ask NXP about plan to develop
  compact model within Modern
• D2.3.4 (M36)   Report on high-level models,
  both analytical and graphical , for PV of in
  Non-Volatile-Memory devices (NMX)
• AI change title   Report on high-level models,
  both analytical and graphical , for PV of devices
  in Non-Volatile-Memory technologies (NMX)

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MODERN General MeetingTask 2.4 summary

• Catania, Nov. 9-10 2010

32
Reliability T2.4 Deliverables
Ref Deliverable/ Contributors Due date
D2.4.1 Specification of considered degradation effects, modeling approaches and device parameters (UNGL, TUW) M6 (Done)
D2.4.2 Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA) M24
D2.4.3 Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA) M33
Task Leader Jong-mun.park_at_austriamicrosystems.com
 
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MODERN General Meetings Catania, Nov. 9 10, 2010
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WP2/ Task 2.4 contributions

Effects -gt Technologies HCI NBTI TDDB RTN/Trapping/ De-trapping SBD/BD
HV mos AMS TUW AMS TUW
65nm cmos UNCA (NXP)
45nm cmos UNGL UNCA (NXP) UNGL UNGL
NVM UNET (NMX)
Thin Si IMEP
AI(all, end 2010) WP2 and per Task work matrix
completion
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MODERN General Meetings Catania, Nov. 9 10, 2010
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T2.4 Review Summary

• Activity done so far, with highlights on
  technical results, and dissemination
• - D2.4.1 deliverable done.
• - NBTI and HC data (0.35 µm LV-CMOS
  HV-CMOS) available for TCAD simulations.
• - Initial physics-based analytical model
  for NBTI to implement in circuit simulator.
• - Time dependent modeling of degradation
  for NBTI HC.
• Plan for D2.4.2 deliverable (M24)
• - TCAD reliability simulations focused on
  HV-CMOS.
• - Hot-Carrier lifetime model for HV-CMOS by
  modified Hu-model.
• - Threshold Voltage Mismatch Induced by
  Hot-Carrier in 65 and 45 nm Technology Node.
• Plan for D2.4.3 deliverable (M33)
• - Statistical compact Models will be
  extracted at different levels of NBTI and PBTI.
• - Time dependence of the statistical compact
  models will be provided based on NBTI and
• PBTI models of trap charge as a function
  of time.
• - Analytical NBTI and HC model developments
  for LV- HV-CMOS.

34
MODERN General Meetings Catania, Nov. 9 10, 2010
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NBTI Hot-Carrier Activities (1)

• Extraction of capture/emission time maps
• Compact modeling using RC circuits

35
MODERN General Meetings Catania, Nov. 9 10, 2010
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NBTI Hot-Carrier Activities(2)

• SE-mechanism
• ME-mechanism
• Idlin degradation represented by the compact
  model

36
MODERN General Meetings Catania, Nov. 9 10, 2010
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Threshold Voltage Mismatch Induced by
Hot-Carrier in 65 and 45 nm Technology Node
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MODERN General Meetings Catania, Nov. 9 10, 2010
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Lifetime Models for High-Voltage NMOS
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MODERN General Meetings Catania, Nov. 9 10, 2010
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WP2 action items

• Task 2.4 Statistical Reliability
• D2.4.2 (M24)  Hardware results of aging
  measurements available, on planar bulk CMOS
  technologies (AMS, TUW, UNET, UNCA)
• gt AI (UNCA, working with NXP) addition of
  sub-Vt slope to Vt figure for HCI effects
• D2.4.3 (M33)  Implementation of statistical
  degradation effects into aging models, hardware
  calibration of degradation effects (IMEP, AMS,
  TUW, UNGL, UNET, UNCA)
• AI (AMS, TUW) Implementation of process
  variations in NBTI/HCI degradation compact models
  for HV devices remains challenging task (physics
  complexity) nevertheless achievable with some
  approximations to physics
• AI (UNGL) UNGL to clarify contents of
  contribution to NBTI/HCI compact models

40
MODERN General MeetingTask 2.5 summary

• Catania, Nov. 9-10 2010

41
Compact Modeling T2.5 Deliverables
Ref Deliverable/ Contributors Due date
D2.5.1 PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2) , and Non-Volatile-Memory technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN technologies (ST-I). State-of-the-art based statistical models, based on hardware and/or TCAD M18 DONE
D2.5.2 Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS) M30
D2.5.3 PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2) Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET) M33
Task Leader paolo.pavan_at_unimore.it
14/05/2015
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Variations in statistical models sources
Local Statistical
Line edge roughness
Poly Si granularity
Channel dopants
Source A.Asenov
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UNGL Deliverable 2.5.1

• Extraction of accurate uniform compact models, DC
  and AC

NMOS IDVD
Capacitance fit atVD0V
NMOS with substrate bias
Capacitance fit atVD1.1V
MODERN General Meetings Catania, Nov. 9 10, 2010
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UNGL Deliverable 2.5.1

• Selection of optimal statistical parameter set
  and statistical compact model extraction
• Preservation of parameter correlations

NMOS and PMOS parametercorrelations
Distribution of fitted error for different
parameter sets
MODERN General Meetings Catania, Nov. 9 10, 2010
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Statistical Models for Circuit Simulation
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T2.5 action items

• Task 2.5 compact modeling
• D2.5.2 (M30)   Statistical PV-aware models for
  planar bulk CMOS generation devices (down to
  32nm) (POLI, UNGL, UNET, NXP, AMS)
• AI (STF2, Dec 2010) To clarify if D2.5.3
  contribution (45nm Analog) effectively transforms
  into D2.5.2 contribution (32nm Digital)
• D2.5.3 (M33)  PV-aware circuit-level models
  for 45nm analog CMOS technology (ST-F2). Modeling
  of additional variability sources of
  3-dimensional device architectures, for new
  device architectures for 22nm (LETI, UNGL, UNET)
• gt AI(WP leader, same as AI as D2.2.5, Nov
  2010) to contact LETI, cc UNGL on demonstrator
  devices (FDSOI, Finfets?,) and associated
  templates. Backup template devices already
  available at UNGL. Need decision latest Feb
  2011.

47
Contents

• WP2 introduction
• Task 2.1 to 2.5 summary
• Matrix, Gantt chart, relation with other Wps
• Action points from meeting

48
WP2 meetingDomain overview per task and partner
Technologies Process simulation Device simulation Electrical Charact. Reliability Compact Modeling
Task 2.1 2.2 2.3 2.4 2.5
HVMOS AMS TUW AMS TUW AMS TUW
Planar CMOS 65nm UNCA
45nm UNGL POLI SNPS (STF2) IMEP STF2 UNGL UNGL POLI STF2 NXP
32nm UNGL POLI (STF2) IMEP STF2 UNGL
NVM 41nm UNET NMX SNPS UNET NMX UNET (NMX) UNET NMX
FDSOI IMEP (STF2) LETI IMEP LETI
Finfets, MUG, GAA STF2 NXP IMEP
SiC Power MOS STI STI STI
AlGaN-GaN HEMT STI STI STI

• PV aware tools and methods are of common
  interest they are developped and applied to a
  wide spectrum of technologies (Project book rev2
  v2.4.1).
• Significant communalities of technology targets,
  except different ones for Process and Device
  simulation.
• (not funded)

MODERN General Meetings Catania, Nov. 9 10, 2010
49
WP2/ Task 2.4 contributions

Effects -gt Technologies HCI NBTI TDDB RTN/Trapping/ De-trapping SBD/BD
HV mos AMS TUW AMS TUW
65nm cmos UNCA (NXP)
45nm cmos UNGL UNCA (NXP) UNGL UNGL
NVM UNET (NMX)
Thin Si IMEP
AI(all, end 2010) WP2 and per Task work matrix
completion
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MODERN General Meetings Catania, Nov. 9 10, 2010
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WP2 meeting Gantt chart
AI(all) requires completion (links with other
WPs), and review by email within 2 months
51
WP2 action items

• WP2
• Need to Complete WP2 matrix 1 matrix per task
• Need to Complete Gantt chart
• AI (all, Jan 2010).
• WP leader to send email for feedback collection
  Nov 2010.
• WP2 members to feedback to Task Leaders, who will
  compile and update per task.

52
Contents

• WP2 introduction
• Task 2.1 to 2.5 summary
• Matrix, Gantt chart, relation with other Wps
• Backup List of Action points from meeting

53
WP2 action items

• WP2
• Need to Complete WP2 matrix 1 matrix per task
• Need to Complete Gantt chart
• gt AI (all, Jan 2010). WP leader to send email
  for feedback collection Nov 2010. WP2 members to
  feedback to Task Leaders, who will compile and
  update per task.
• Task 2.1 Process simulation
• D2.1.2 (M27)   Enhanced process simulation
  including treatment of PV for Discrete Power
  Device, HV-CMOS, SiC, GaN/AlGaN technologies,
  interfaced to commercial TCAD tools (ST-I, AMS,
  TUW) 
• AI (STI, AMS, M27) HVMOS and AsGaN-SiC device
  sensitivity analysis to Process variations to be
  validated on HW data available from D2.3.2
• Task 2.2 Device simulation
• D2.2.4 (M24)  Forecast of the magnitude of
  statistical variability in 32nm planar bulk CMOS
  devices via device simulation (UNGL, IMEP, UNET)
• AI (STF2, Nov 2010) to provide TCAD decks.
  5-way NDA between UNGL-UNET-SNPS-POLI-ST applies.

54
WP2 action items

• Task 2.2
• D2.2.5 (M27)  TCAD based assessment of PV
  effects of potential 22nm device architectures
  (UNGL)
• gt AI (WP leader, Nov 2010) contact LETI on
  demonstrator devices (FDSOI, Finfets?,) and
  associated templates. Backup template devices
  already available at UNGL. Need decision latest
  Feb 2011.
• D2.2.6 (M36)  Sensitivity analysis of Non
  Volatile Memory device performance as a function
  of individual trap position (NMX,UNET) . Toolbox
  (methodologies, models, tools) to make dominant
  variability effects accessible to industrial
  usage of TCAD. Outlook to 16nm device
  architecture robustness using MASTAR (UNGL,
  STF2)
• gt AI(T2.2 Leader) Contact SNPS if they intend
  to contribute to toolbox

55
WP2 action items

• Task 2.3 Characterization and simulation
  verification
• D2.3.2 (M18)/D2.3.4 (M36)  1/f noise
  dispersion
• gt AI (WP leader) Ask NXP about plan to develop
  compact model within Modern
• D2.3.4 (M36)   Report on high-level models,
  both analytical and graphical , for PV of in
  Non-Volatile-Memory devices (NMX)
• AI change title   Report on high-level models,
  both analytical and graphical , for PV of devices
  in Non-Volatile-Memory technologies (NMX)
• Task 2.4 Reliability
• D2.4.2 (M24)  Hardware results of aging
  measurements available, on planar bulk CMOS
  technologies (AMS, TUW, UNET, UNCA)
• gt AI (UNCA, working with NXP) addition of
  sub-Vt slope to Vt figure for HCI effects
• D2.4.3 (M33)  Implementation of statistical
  degradation effects into aging models, hardware
  calibration of degradation effects (IMEP, AMS,
  TUW, UNGL, UNET, UNCA)
• AI (AMS, TUW) Implementation of process
  variations in NBTI/HCI degradation compact models
  for HV devices (Challenging, nevertheless
  achievable with some approximations to physics)
• AI (UNGL) UNGL to clarify contribution to
  NBTI/HCI compact models

56
WP2 action items

• Task 2.5 compact modeling
• D2.5.2 (M30)   Statistical PV-aware models for
  planar bulk CMOS generation devices (down to
  32nm) (POLI, UNGL, UNET, NXP, AMS)
• AI (STF2) Clarifies if D2.5.3 contribution (45nm
  Analog) transforms into D2.5.2 contribution (32nm
  Digital)
• D2.5.3 (M33)  PV-aware circuit-level models
  for 45nm analog CMOS technology (ST-F2). Modeling
  of additional variability sources of
  3-dimensional device architectures, for new
  device architectures for 22nm (LETI, UNGL, UNET)
• gt AI(WP leader, same as AI as D2.2.5, Nov
  2010) contact LETI on demonstrator devices
  (FDSOI, Finfets?,) and associated templates.
  Backup template devices already available at
  UNGL. Need decision latest Feb 2011.