PROGRAMMABLE LOGIC DEVICES PLD

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PROGRAMMABLE LOGIC DEVICES (PLD)
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PLD

• Problems by Using Basic Gates
• Many components on PCB
• As no. of components rise, nodes interconnection
  complexity grow exponentially
• Growth in interconnection will cause increase in
  interference, PCB size, PCB design cost, and
  manufacturing time

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PLD 1

• The purpose of a programmable logic device is to
  permit elaborate digital logic designs to be
  implemented by the user in a single device.
• Many of them can be erased electrically and
  reprogrammed with a new design, making them very
  well suited for academic and prototyping uses.
• Types of Programmable Logic Devices
• SPLDs (Simple Programmable Logic Devices)
• ROM (Read-Only Memory)
• PLA (Programmable Logic Array)
• PAL (Programmable Array Logic)
• GAL (Generic Array Logic)
• CPLD (Complex Programmable Logic Device)
• FPGA (Field-Programmable Gate Array)

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PLD 2

• The first three varieties are quite similar to
  each other
• They all have an input connection matrix, which
  connects the inputs of the device to an array of
  AND-gates.
• They all have an output connection matrix, which
  connect the outputs of the AND-gates to the
  inputs of OR-gates which drive the outputs of the
  device.
• The gate array is significantly different and
  will be described later.

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PLD 3

• The differences between the first three
  categories are these
• 1. In a ROM, the input connection matrix is
  hardwired. The user can modify the output
  connection matrix.
• In a PAL the output connection matrix is
  hardwired. The user can modify the input
  connection matrix.
• In a PLA the user can modify both the input
  connection matrix and the output connection
  matrix.

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General structure of PLDs.
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Buffer/inverter
(a) Symbol. (b) Logic equivalent.
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Programming by blowing fuses.
(a) Before programming. (b) After
programming.
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OR PLD Notation
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AND PLD Notation
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PLD notation.

• (a) Unprogrammed and-gate.
• (b) Unprogrammed or-gate.
• (c) Programmed and-gate realizing the term ac.
• (d) Programmed or-gate realizing the term a b.
• (e) Special notation for an and-gate having all
  its input fuses intact.
• (f) Special notation for an or-gate having all
  its input fuses intact.
• (g) And-gate with non-fusible inputs.
• (h) Or-gate with non-fusible inputs.

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PROM Notation
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• A 2n ? m PROM.
• Logic diagram.
• (b) Representation in PLD notation.

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Using a PROM for logic design
(a) Truth table. (b) PROM
realization.
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Logic diagram of an n ? p ? m PLA
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Example of combinational logic design using a PLA.
(a) Maps showing the multiple-output prime
implicants. (b) Partial covering of the f1 and f2
maps. (c) Maps for the multiple-output minimal
sum. (d) Realization using a 3 ? 4 ? 2 PLA.
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Exclusive-or-gate with a programmable fuse
(a) Circuit diagram. (b)
Symbolic representation.
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General structure of a PLA having true and
complemented output capability
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Karnaugh maps for the functions f1(x,y,z)
?m(1,2,3,7) and f2(x,y,z) ?m(0,1,2,6)
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Two realizations of f1(x,y,z) ?m(1,2,3,7) and
f2(x,y,z) ?m(0,1,2,6). (a) Realization based on
f1 and 2 (b) Realization based on 1 and 2
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A simple four-input, three-output PAL device.
Figure 5.62
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An example of using a PAL device to realize two
Boolean functions. (a) Karnaugh maps. (b)
Realization. Figure 5.63
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