ITRS-2001 Design ITWG July 18, 2001 Europe: W. Weber Japan: Y. Furui, T. Kadowaki, H. Taguchi, K. Uchiyama USA: A. Kahng, K. Kolwicz

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ITRS-2001 Design ITWGJuly 18, 2001Europe W.
WeberJapan Y. Furui, T. Kadowaki, H. Taguchi,
K. UchiyamaUSA A. Kahng, K. Kolwicz
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System Drivers Chapter

• Define IC products that drive mfg, design
  technologies
• Replace the 1999 SOC Chapter
• ORTCs SDs consistent framework for tech
  requirements
• Four system drivers
• (HVC) MPU traditional processor core
• SOC (focus on ASIC-LP, high-pins,
  high-signaling network driver)
• AM/S four basic circuits and FOMs
• (HVC) DRAM
• Each driver section
• Nature, evolution, formal definition of this
  driver
• What market forces apply to this driver ?
• What technology elements (process, device,
  design) does this drive?
• Key figures of merit, and roadmap
• Working text material (handout) (MPU) , (SOC) ,
  AMS
• Inputs from Test, AP, Litho/PIDS/FEP,
  Interconnect

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MPU Driver

• Old MPU model 3 flavors
• New MPU model - 2 flavors
• Cost-performance at production (CP)
• 140 mm2 die, desktop
• High-performance at production (HP)
• 310 mm2 die, server
• Both have multiple cores (helper engines),
  on-board L3 cache,
• Multi-cores more dedicated, less
  general-purpose logic driven by power and reuse
  considerations reflect convergence of MPU and
  SOC
• Doubling of transistor counts is each per each
  node, NOT per each 18 months
• Clock frequencies stop doubling with each node

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Example Supporting Analyses (MPU)

• Diminishing returns
• Pollacks Rule In a given process technology,
  new microarchitecture takes 2-3x area of previous
  generation one, and provides only 50 more
  performance
• Corroboration SPECint/MHz, SPECfp/MHz,
  SPECint/Watt all decreasing
• Power knob running out
• Speed Power
• Large switching currents, large power surges on
  wakeup, IR drop control issues all limited by AP
  roadmap (e.g., improvement in bump pitch, package
  power)
• Power management 2500 improvement needed by
  2016
• Speed knob running out (new clock frequency
  model)
• Historically, 2x clock frequency every node
• 1.4x/node from device scaling but running into
  tox, other limits (PIDS)
• 1.4x/node from fewer logic stages (from 40-100
  down to around 14 FO4 INV delays)
• Clocks cannot be generated with period lt 6-8 FO4
  INV delays
• Pipelining overhead (1-1.5 FO4 INV delay for
  pulse-mode latch, 2-3 for FF)
• Around16 FO4 INV delays is limit for clock period
  in core (L1 access, 64b add)
• Cannot continue 2x frequency per node trend in
  ITRS

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Example Supporting Analyses (MPU)

• Logic Density Average size of 4t gate 32MP2
  320F2
• MP lower-level contacted metal pitch
• F min feature size (technology node)
• 32 8 tracks standard-cell height times 4 tracks
  width (average NAND2)
• Additional whitespace factor 2x (i.e., 100
  overhead)
• Custom layout density 1.25x semi-custom layout
  density
• SRAM Density (used in MPU)
• bitcell area (units of F2) near flat 223.19F
  (um) 97.748
• peripheral overhead 60
• memory content is increasing (driver power) and
  increasingly fragmented
• will see paradigm shifts in architecture/stacking
  eDRAM, 1-T SRAM, 3D integ
• Significant SRAM density increase, slight Logic
  density decrease, compared to 1999 ITRS
• 130nm node old ASIC logic density 13M tx/cm2,
  new 11.6M tx/cm2
• 130nm node old SRAM density 70M tx/cm2, new
  140M tx/cm2
• Chief impact power densities, logic-memory
  balance on chip

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SOC-LP Driver (STRJ)

• Power gap
• Must reduce dynamic and static power to avoid
  zero logic content limit
• Hits low-power SOC before hits MPU
• SOC degree of freedom low-power (not high-perf)
  process
• SOC-LP model drives ASIC-LP (PIDS) device model
• Lgate lags high-performance devices by 2 years
• Accompanying device parameter changes
• Vth higher (up to .5 x Vdd limit)
• Ig, Ioff starts at 100pA/um (L(Operating)P),
  1pA/um (L(STandby)P)
• Tox higher
• Slower devices (higher CV/I)
• Four LP device flavors Design still faces
  40-1000/node static power management challenge,
  and must address multi (Vt,tox,Vdd)
• SOC-LP driver low-power PDA
• Composition CPU cores, embedded cores,
  SRAM/eDRAM
• Roadmap for IO bandwidth, processing power,
  GOPS/mW efficiency
• Die size grows at 20 per node

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SOC-LP Driver Model

• Required performance trend of SOC-LP PDA driver
• Drives PIDS/FEP LP device roadmap, Design power
  management challenges

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Mixed-Signal Driver(Europe)

• Ralf Brederlow, Stephane Donnay,Joseph
  Sauerer, Maarten Vertregt,Piet Wambacq, and
  Werner Weber
• Infineon Technologies, IMEC, Fraunhofer-Instuti
  tut for Integrated Circuits , Philips
  Semiconductor

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Overview

• Today, the digital part of circuits is most
  critical for performance and is dominating chip
  area
• But in many new IC-products the mixed-signal part
  becomes important for performance and cost
• This shift in paradigms leads to the need for a
  definition of the analog boundary conditions in
  the design part of the ITRS roadmap
• The goal is to define criteria for needs of
  future analog/RF circuit performance and compare
  it to device parameters
• choose critical and important analog/RF circuits
• identify circuit performance needs
• and related device parameter needs

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Concept for the Mixed-Signal-Roadmap

• Figures of merit for four important basic analog
  building blocks are defined and estimated for
  future circuit design
• From these figures of merit related future device
  parameter needs are estimated (PIDS-table
  partially owned by design)

Roadmap for basic analog / RF circuits
Roadmap for device parameter (needs)

A/D-Converter
Lmin 2001 2015
Low-Noise Amplifier
Voltage-Controlled Oscillator
mixed-signal device parameter
Power Amplifier
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Figure of Merit for LNAs

• LNA performance

• dynamic range
• power consumption

G gain NF noise figure IIP3 third
order intercept point P dc supply
power f frequency
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Figure of Merit for VCOs

• VCO performance

• timing jitter
• power consumption

f0 carrier frequency Df frequency offset from
f0 LDf phase noise P supply power
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Figure of Merit for PAs

• PA performance

• output power
• power consumption

Pout output power G gain PAE power
added efficiency IIP3 third order intercept
point f frequency
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Figure of Merit for ADCs

• ADC performance

• dynamic range
• bandwidth
• power consumption

ENOB0 effective number of bits fsample sampling
frequency ERBW effective resolution
bandwidth P supply power
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Mixed-Signal Device Parameters
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Mixed-Signal Market Drivers
System drivers for mass markets can be identified
from the FoM approach
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Design Chapter Outline

• Introduction
• Scope of design technology
• Complexities (silicon, system, design process)
• How design technology is driven by System Drivers
• Design Grand Challenges
• Details of challenges/needs and potential
  solutions (metrics)
• One section for each of
• Design Process (quality/cost model )
• Functional Verification (escapes, fault
  tolerance)
• System-Level (embedded software productivity,
  reuse, quality)
• Logical/Physical/Circuit (power management,
  AM/S circuit FOMs)
• Test (BIST, )
• In each section
• Overview of detailed issues and challenges
• Near-term / long-term needs related to driver
  classes
• Key quality metrics (tables or figures)

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Design Grand Challenges gt 65nm

• Scaling of maximum-quality design implementation
  productivity
• Overall design productivity of quality-
  (difficulty-) normalized functions on chip must
  scale at 2x / node
• Reuse (including migration) of design,
  verification and test effort must scale at gt
  2x/node
• Develop analog and mixed-signal synthesis,
  verification and test
• Embedded software productivity
• Power Management
• Off-currents in low-power devices increase
  10x/node design technology must maintain
  constant static power
• Power dissipation for HP MPU exceeds package
  limits by 25x in 15 years design technology must
  achieve power limits
• Power optimizations must simultaneously and fully
  exploit many degrees of freedom - multi-Vt,
  multi-Tox, multi-Vdd in core - while guiding
  architecture, OS and software
• Deeper integration of Design technology with
  other ITRS technology areas
• Example Die-package co-optimization
• Example Design for Manufacturability (sharing
  variability burden with Litho/PIDS/FEP and
  Interconnect, reduction of system NRE cost)
• Example Design for Test

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Design Grand Challenges lt 65nm

• (Three Grand Challenges from gt 65nm, and)
• Noise Management
• Lower noise headroom especially in low-power
  devices coupled interconnects supply voltage IR
  drop and ground bounce thermal impact on device
  off-currents and interconnect resistivities
  mutual inductance substrate coupling
  single-event upset (alpha particle) increased
  use of dynamic logic families
• Modeling, analysis and estimation at all levels
  of design
• Error-Tolerant Design
• Relaxing 100 correctness requirement may reduce
  manufacturing, verification, test costs
• Both transient and permanent failures of signals,
  logic values, devices, interconnects
• Novel techniques adaptive and self-correcting /
  self-repairing circuits, use of on-chip
  reconfigurability

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Design Cost Analysis

• Largest possible ASIC design cost model
  (Dataquest)
• engineer cost per year increases 5 per year
  (181,568 in 1990)
• EDA tool cost per year increases 3.9 per year
  (99,301 in 1990)
• Gates in largest ASIC/SOC design (.25M in 1990,
  250M in 2005)
• Logic Gates constant at 70
• Engineers / Million Logic Gates decreasing from
  250 in 1990 to 5 in 2005
• Productivity due to 8 major Design Technology
  innovations (3.5 of which are still unavailable)
  RTL methodology In-house PR Tall-thin
  engineer Small-block reuse Large-block reuse
  IC implementation suite Intelligent testbench
  ES-level methodology
• Small refinements (1) memory content (2) other
  design NRE (mask cost, etc.)
• Engineers per ASIC design still rising 20x in 15
  years despite assumed 50x improvement in designer
  productivity

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Design Cost and Quality Requirement

• Design cost of largest ASIC rises despite major
  DT innovations
• Other Dataquest s confirm slight increase in
  memory content
• Must complement with requirements for design
  quality

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Design Quality Model

• Normalized transistor quality model normalizes
• speed, power, density in a given technology
• analog vs. digital
• custom vs. semi-custom vs. generated
• first-silicon success
• other simple / complex clocking,
  verification/test effort and coverage,
  manufacturing cost,
• Design process quality model in development
• Many private commercial and/or in-house analogues
• Survey methodology being used (US, MARCO GSRC)