The FC16 Forth Core

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The FC16 Forth Core

• Lab 7
• Module F4.1

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(No Transcript)
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Lab 7
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Data Stack Instructions
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Funit16 Instructions (fcode lower 6 bits of
opcode)
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Funit16 Instructions (cont.) (fcode lower
6-bits of opcode)
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Return Stack, Memory Access, and I/O Instructions
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Literal and Transfer Instructions
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Multiplication and Division Instructions
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Multiplication
1101 x1011 1101 1101 100111
0000 100111 1101 10001111
13 x11 13 13 143 8Fh
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Multiplication
1101 x1011 1101 1101 100111
0000 100111 1101 10001111
1101 00001011 01101101 adsh 1101 10011110 adsh
1001111 sh 1101 10001111 adsh
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Multiplication
UM ( u1 u2 -- upL upH )
T
N
N2
mpp (multiply partial product) if N(0) 1
then adsh else sh end if
UM ( u1 u2 - upL upH ) 0 4 FOR mpp
NEXT ROT_DROP
All other signed and unsigned multiplication can
be derived from UM
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16 x 16 32 Multiply Instruction
UM ( u1 u2 - upL upH ) 0 16 FOR mpp
NEXT ROT_DROP
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Testing Multiply Instruction
MAIN ( -- ) BEGIN waitB4 S_at_ \ get
u1LO waitB4 S_at_ \ get u1HI waitB4 S_at_ \ get
u2LO waitB4 S_at_ \ get u2HI waitB4 UM \
multiply DIG! \ display upH waitB4 DIG! \
display upL AGAIN
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variable AVector STD_LOGIC_VECTOR (width
downto 0) variable BVector STD_LOGIC_VECTOR
(width downto 0) variable CVector
STD_LOGIC_VECTOR (width downto 0) variable
yVector STD_LOGIC_VECTOR (width downto 0)
variable y_tmp STD_LOGIC_VECTOR (width-1 downto
0) variable y2_tmp STD_LOGIC_VECTOR (width-1
downto 0) variable yvec0 STD_LOGIC
begin
AVector '0' a BVector '0'
b CVector '0' c y_tmp
false y2_tmp false yVector '0'
false
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mpp (multiply partial product) if N(0) 1
then adsh else sh end if
when "11110" gt -- mpp if b(0) '1' then
yVector AVector CVector else yVector
AVector end if y lt yVector(width downto
1) y2 lt yVector(0) b(width-1 downto 1)
T
N
N2
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Division
10
1010
13 135 13 05
1101 10000111
1101 00111 0000 01111 1101 00101 0000
0101
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Division 8-bit/4-bit 44
1010
_10000111 1101
numer80 denom30
1101 10000111
1101 00111 0000 01111 1101 00101 0000
0101
If denom lt numer74 then overflow (quotient
wont fit in 4 bits)
Let T numer84 N numer30 N2
denom30
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Division 8-bit/4-bit 44
T
N
1010
sll
100001110 1101
1101 10000111
1101 00111 0000 01111 1101 00101 0000
0101
N2
for I in 0 to 3 loop sll T N if T84 gt
N2 then T T - (0 N2) N(0)
1 end if end loop
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Division 8-bit/4-bit 44
T
N
1010
sll
100001110 1101
1101 10000111
N2
1101 00111 0000 01111 1101 00101 0000
0101
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Division
N2
T
N
UM/MOD ( unumL unumH udenom -- urem uquot )
N2
T
N
-ROT 4 FOR SHLDC NEXT denom quot
rem ROT_DROP_SWAP
All other signed and unsigned division operations
can be derived as WHYP words from UM/MOD
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when "11111" gt -- shldc yVector a
b(width-1) y2_tmp b(width-2 downto 0)
'0' if yVector gt CVector then yVector
yVector - CVector y2_tmp(0) '1' end
if
y lt yVector(width-1 downto 0) y2 lt y2_tmp
for I in 0 to 3 loop sll T N if T84 gt
N2 then T T - (0 N2) N(0)
1 end if end loop
T
N
sll
100001110 1101
N2
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32 / 16 1616 Division
UM/MOD ( unL unH ud -- ur uq ) -ROT 16
FOR shldc NEXT ROT_DROP_SWAP
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Testing Divide Instruction
MAIN ( -- ) BEGIN waitB4 S_at_ \ get
unLLO waitB4 S_at_ \ get unLHI waitB4 S_at_ \ get
unHLO waitB4 S_at_ \ get unHHI waitB4 S_at_ \
get udLO waitB4 S_at_ \ get udHI waitB4 UM/MOD \
divide Dig! \ display uq waitB4 Dig! \
display ur AGAIN