ECE%20601%20-%20Digital%20System%20Design%20

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ECE 551 Digital System Design Synthesis
Lecture Set 7 7.1 Coding for if and case
(In separate file) 7.2 Coding logic
building blocks 7.3 High-Performance
Coding (In separate file)

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ECE 551 - Digital System Design Synthesis
Lecture 7.2 Coding for Synthesis of
Combinational Logic - Coding Logic Building Blocks

• Overview
• Premise
• Basic coding for if and case
• Synopsis case directives
• Late signal arrival coding for if and case
• Data, Control
• Coding Logic Building Blocks
• Decoder, Priority Encoder, Reduction XOR,
  Multiplexer
• High-Performance Methods
• Datapath Duplication, Operator in if condition
• General Coding Issues
• Resource Sharing
• Arithmetic Expression Optimization

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Decoder

• Decoder using indexing
• Example 3-1 GHCS
• Decoder using for loop
• Example 3-3 GHCS
• Comparison
• Table 3-1 - Timing
• Table 3-2 - Area
• Table 3-3 - Compile Time

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Decoder Using Indexing in Verilog
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Decoder Using Loop in Verilog
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Decoder Verilog Timing Comparison
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Decoder Verilog Area Comparison
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Decoder Verilog Compile Time Comparison
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Priority Encoder

• Priority encoder using for loop starting at
  lowest priority bit
• Example 3-5 GHCS
• Figure 3-4 - Chain structure
• Priority encoder using tree structure
• Verilog not shown
• Figure 3-5 - Tree structure
• Comparison
• Table 3-4 - Timing
• Table 3-5 - Area
• Table 3-6 - Compile Time

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Priority Encoder Verilog Loop - 1
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Priority Encoder Verilog Loop - 2
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Priority Encoder Loop Circuit

• Very long delay due to cascades

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Priority Encoder Tree Verilog
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Priority Encoder Tree Circuit
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Reduction XOR

• Reduction XOR chain
• Example 3-8 GHCS
• Figure 3-7 GHCS
• Reduction XOR tree
• Example 3-10 GHCS
• Figure 3-8 GHCS
• Note
• Design Compiler can convert chain description to
  tree implementation if no intermediate points
  accessed in the chain. Thus, best to use tree
  structure.
• OR chains with intermediate points become tree
  implementations.

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Reduction XOR Verilog Loop
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Reduction XOR Verilog Loop

• Delay long due to cascade

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Reduction XOR Verilog Tree - 1
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Reduction XOR Verilog Tree - 2
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Reduction XOR Verilog Tree - 3
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Reduction XOR Circuit Tree

• Delay reduced by 40 (from 5 to 3 XOR levels)

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Multiplexer

• Multiplexer chain
• Example 3-12 GHCS
• Figure 3-9 GHCS
• Multiplexer tree
• Example 3-14 GHCS
• Figure 3-10 GHCS
• Comparison
• Table 3-7 - Timing
• Table 3-8 - Area

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Multiplexer Chain Verilog
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Multiplexer Chain Circuit

• Long delay results from the cascade

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Multiplexer Tree Verilog - 1
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Multiplexer Tree Verilog - 2
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Multiplexer Tree Verilog - 3
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Multiplexer Tree Verilog - 4
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Multiplexer Tree Circuit
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Multiplexer Synth Comparison - 1
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Multiplexer Synth Comparison - 1
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Summary

• Area, timing, and compile time are coding
  dependent
• Indexing and loops give different results
• If delay is an issue, target tree rather than
  cascade circuits
• Tree may also improve area