Title: ECE%20601%20-%20Digital%20System%20Design%20
1ECE 551 Digital System Design Synthesis
Lecture Set 7 7.1 Coding for if and case
(In separate file) 7.2 Coding logic
building blocks 7.3 High-Performance
Coding (In separate file)
2ECE 551 - Digital System Design Synthesis
Lecture 7.2 Coding for Synthesis of
Combinational Logic - Coding Logic Building Blocks
- Overview
- Premise
- Basic coding for if and case
- Synopsis case directives
- Late signal arrival coding for if and case
- Data, Control
- Coding Logic Building Blocks
- Decoder, Priority Encoder, Reduction XOR,
Multiplexer - High-Performance Methods
- Datapath Duplication, Operator in if condition
- General Coding Issues
- Resource Sharing
- Arithmetic Expression Optimization
3Decoder
- Decoder using indexing
- Example 3-1 GHCS
- Decoder using for loop
- Example 3-3 GHCS
- Comparison
- Table 3-1 - Timing
- Table 3-2 - Area
- Table 3-3 - Compile Time
4Decoder Using Indexing in Verilog
5Decoder Using Loop in Verilog
6Decoder Verilog Timing Comparison
7Decoder Verilog Area Comparison
8Decoder Verilog Compile Time Comparison
9Priority Encoder
- Priority encoder using for loop starting at
lowest priority bit - Example 3-5 GHCS
- Figure 3-4 - Chain structure
- Priority encoder using tree structure
- Verilog not shown
- Figure 3-5 - Tree structure
- Comparison
- Table 3-4 - Timing
- Table 3-5 - Area
- Table 3-6 - Compile Time
10Priority Encoder Verilog Loop - 1
11Priority Encoder Verilog Loop - 2
12Priority Encoder Loop Circuit
- Very long delay due to cascades
13Priority Encoder Tree Verilog
14Priority Encoder Tree Circuit
15Reduction XOR
- Reduction XOR chain
- Example 3-8 GHCS
- Figure 3-7 GHCS
- Reduction XOR tree
- Example 3-10 GHCS
- Figure 3-8 GHCS
- Note
- Design Compiler can convert chain description to
tree implementation if no intermediate points
accessed in the chain. Thus, best to use tree
structure. - OR chains with intermediate points become tree
implementations.
16Reduction XOR Verilog Loop
17Reduction XOR Verilog Loop
- Delay long due to cascade
18Reduction XOR Verilog Tree - 1
19Reduction XOR Verilog Tree - 2
20Reduction XOR Verilog Tree - 3
21Reduction XOR Circuit Tree
- Delay reduced by 40 (from 5 to 3 XOR levels)
22Multiplexer
- Multiplexer chain
- Example 3-12 GHCS
- Figure 3-9 GHCS
- Multiplexer tree
- Example 3-14 GHCS
- Figure 3-10 GHCS
- Comparison
- Table 3-7 - Timing
- Table 3-8 - Area
23Multiplexer Chain Verilog
24Multiplexer Chain Circuit
- Long delay results from the cascade
25Multiplexer Tree Verilog - 1
26Multiplexer Tree Verilog - 2
27Multiplexer Tree Verilog - 3
28Multiplexer Tree Verilog - 4
29Multiplexer Tree Circuit
30Multiplexer Synth Comparison - 1
31Multiplexer Synth Comparison - 1
32Summary
- Area, timing, and compile time are coding
dependent - Indexing and loops give different results
- If delay is an issue, target tree rather than
cascade circuits - Tree may also improve area