???? (Cont), ?????ILP

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???? (Cont), ?????ILP
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Review Tomasulo

• ?????????????????
• ???????
• ????????????????????????
• ?????????
• Out-of-order execution ? out-of-order completion!

• ?????????
• ????????????,??????
• ????????????????
• Scoreboard ?Tomasula
• Tomasula ????
• Dynamic scheduling
• Register renaming---???WAW,WAR??
• Load/store disambiguation
• ???????
• ??
• ????CDB
• ?????Common Data Bus

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????????

• ???????????????????
• ????????????????????
• ????????,?????RAW?WAR??
• ???????????????????????
• ?????? rename table ,??????????????????
• ????????????RS?.
• ????????2x ?????x????.

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?????????

• ????????????????
• ???????????,???????????????????.
• ?????????????????,????
• ??
• DIVD F10, F0, F2
• SUBD F4, F6, F8
• ADDD F12, F14, F16
• ??rollback ???????????
• ??????????????
• ??????????????
• ???????????
• ?????????????(???)
• ??????????????????????

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??????????????????!

• ?????????,??????????????????,??????????!
  Loop LD F0 0 R1 MULTD F4 F0 F2 SD F4 0 R
  1 SUBI R1 R1 8 BNEZ R1 Loop
• ???????multd,?????
• ?????????
• ??????,???????????
• ??superscalar??????????

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???????????

• ???????????????????,?????????????????????????????
  ??????
• ??????????????????
• ???????????????,???????????????,??????????????????
  ???????
• ???????????????????????
• ????
• ????????????
• ?????????????????

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????????

• ??????K??????,?????????????

• ??????????,???????????????,???????????????????,???
  ???????????,???????,????????????????????

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???????????????

• ???????K?????,?????????,??????,?????????k-1???????
  ????????????????????p, ????????q??????????????
• ?????????????????,????????????????
• ?????????Static (at compile time) ?????
  Dynamic (at runtime)
• ?????? vs. ??????,????

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Dynamic Branch Prediction

• ????????????????????????
• ?????????
• ??????????
• ??????????????,???????
• ????
• ??BPB(Branch Prediction Buffer)?BHT(Branch
  History Table)???
• 1-bit BHT?2-bit BHT
• Correlating Branch Predictors
• Tournament Predictors Adaptively Combining Local
  and Global Predictors
• High Performance Instruction Delivery
• BTB
• Integrated Instruction Fetch Units
• Return Address Predictors
• Performance ƒ(accuracy, cost of misprediction)
• Misprediction ? Flush Reorder Buffer

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1-bit BHT

• Branch History Table ?????PC?????1-bit BHT
• ?????????????
• ??????
• ?????????10?,??????9?,1????,????????????????,????
  ??????????
• ???? vs. ????
• ?? ??????, 1-bit BHT ???2???????(avg is 9
  iteratios before exit)
• ??????, ????????,?????????
• ?????,?????????,?????????

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2-bit BHT

• ???? 2???????
• Red stop, not taken
• Green go, taken

NT
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BHT Accuracy

• ?????????
• ????
• ????PC?????BHT?,?????????????
• BHT??????
• 4096 ?????????????1 (nasa7, tomcatv) to 18
  (eqntott), spice at 9 and gcc at 12
• ?????,??????????????(in Alpha 21164)

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Correlating Branch Predicator

• ??
• if (aa2) aa0
• if (bb2) bb0
• if (aa!bb)
• ???DLX
• SUBI R3,R1,2
• BNEZ R3,L1 branch b1
  (aa!2)
• ADDI R1,R0,R0 aa0
• L1 SUBI R3,R2,2
• BNEZ R3,L2 branch
  b2(bb!2)
• ADDI R2,R0,R0 bb0
• L2 SUBI R3,R1,R2 R3aa-bb
• BEQZ R3,L3 branch b3
  (aabb)

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Correlating Branches

• ????b3 ???b2 ?b1?????b1?b2?????,?b3?????
• Correlating predictors ? ????????????????????????
  ?
• ??????????????????????
• if (d0)d1
• if (d1) d0
• ???DLX
• BNEZ R1,L1
  branch b1(d!0)
• ADDI R1,R0,1
  d0, so d1
• L1 ADDI R3,R1,-1
• BNEZ R3,L2
  branch b2(d!1)
• ...
• L2

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???????????

• ??d???????0,1,2
• b1 ??????,b2????????
• ????????????????????,???????????

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• ??d?????2?0?????
• ?1-bit???,?????????,T??????,NT???????
• ?????????????,?????100

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Correlating Branches

• ?????1???correlation????????????????????????????
  ??????????????,??????????????????????????
• ?????????????????????????
• ?? (1,1)??????????????????,??????????????????

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• Correlating ???????????,
• ????????d2?,????,???????
• ??(1,1)???,?????????????????1-bit????????
• ???????(m, n),??????m???,?2m????????????,?????????
  n

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Correlating Branches

• (2,2) predictor 2-bit global, 2-bit local

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Tournament Predictors

• Tournament predictors
• ???????
• ????????
• ????????
• ???????
• Use the predictor that tends to guess correctly

history
addr
Predictor B
Predictor A
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Tournament Predictor in Alpha 21264

• Selector4K 2-bit ???????????????????
• Global predictor ??4K?,?????12???????????,??????2
  -bit???
• 12-bit pattern ith bit 0 gt ith prior branch not
  taken ith bit 1 gt ith prior branch taken
• Local predictor ?????
• Top level 1024?10-bit ???,??10-bit?????10????????
  
• Next level ?Top level?????10-bit????1K
  ??????,???3-bit saturating counter ???????
• Total size 4K2 4K2 1K10 1K3 29K
  bits!
• (180,000 transistors)

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of predictions from local predictor in
Tournament Scheme
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Accuracy of Branch Prediction
fig 3.40

• Profile branch profile from last
  execution(static in that in encoded in
  instruction, but profile)

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Accuracy v. Size (SPEC89)
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Simple dynamic prediction Branch Target Buffer
(BTB)

• ?????????BTB???,?????????
• ???????????????,??????????
• ?????????
• ???????,?????PC

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• Determine the total branch penalty for a
  branch-target buffer assuming the penalty cycles
  for individual mispredictions from figure 2.24.
  Make the following assumptions about the
  prediction accuracy and hit rate
• Prediction accuracy is 90 (for instructions in
  the butter)
• Hit rate in the buffer is 90 (for branches
  predicted taken)

Ans. P1 9010 P2 10 BP
(0.090.1)2 0.38
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Review ???????????

• ????????????????????????
• ????????
• ??????????
• ??????????????,???????
• ????
• 1-bit BHT?2-bit BHT
• Correlating Branch Predictors
• Tournament Predictors Adaptively Combining Local
  and Global Predictors
• High Performance Instruction Delivery
• BTB
• Integrated Instruction Fetch Units
• Return Address Predictors
• Performance ƒ(accuracy, cost of misprediction)
• Misprediction ? Flush Reorder Buffer

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Accuracy of Different Schemes
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HW support for More ILP

• ??????????????????????
• if (x) then A B op C else NOP
• ???????,?????,??????
• ??ISA, Alpha, MIPS, PowerPC, SPARC ?ISA ,
  ???????? PA-RISC ???????
• EPIC 64 1-bit ???????????
• ??????(conditional instructions)???
• ?????????,????????
• ????????,???Stall
• ???????????,??????????????????

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????????

• ??????????????? reorder buffer (ROB)
• 3 ?? ????,????, ?
• Reorder buffer ???????? gt ?????????(?RS??)
• ??????????,?ROB?????RS???
• ????????
• ROB?????????????????
• ???????,????????
• ??,??????,???????????,??????,??????

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??????? Tomasulo ??????

• 1. Issueget instruction from FP Op Queue
• ??RS?ROB?????????????????ROB???????,??????RS,?????
  ROB??????RS (this stage sometimes called
  dispatch)
• 2. Executionoperate on operands (EX)
• ???????,???????????,??CDB,??RAW??
• 3. Write resultfinish execution (WB)
• ???????CDB??????????FU??ROB??,??RS??
• 4. Commitupdate register with reorder result
• ?ROB????,??????,??????(????),??????ROB????
• ?????????,??ROB

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• LD F6, 34(R2)
• LD F2, 45(R3)
• MULT F0, F2, F4
• SUBD F8, F6, F2
• DIVD F10, F0, F6
• ADDD F6, F8, F2

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v
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????????? ?????????RAW??

• Question ????????,store,load ??????????
• ????????????? Eg st 0(R2),R5 ld R6,0(R3)
• ??????????ld?
• Store????????????????.
• ?????????????????????.
• ????
• No Speculation ???load??,???????? 0(R2) ? 0(R3)
• Speculation ??????????????? (called dependence
  speculation) ,????????ROB???

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Hardware Support for Memory Disambiguation

• ?????????????????????
• ????(?????)??(????)
• FIFO ordering ?????????store
• ?????load???,????store??????.
• ?load??????,??store??
• ???load??????????store??,?stall?load??
• ??load??????store????,?? memory-induced RAW
  hazard
• ?????? ? ???
• ?????????? ? ???store???ROB??
• ?????????
• ?????store??????,?????WAW ??.

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Memory Disambiguation
Done?
FP Op Queue
ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1
Newest
--
LD F4, 10(R3)
N
Reorder Buffer
F2
ST 10(R3), F5
N
F0
LD F0,32(R2)
N
Oldest
--
ltval 1gt
ST 0(R3), F4
Y
Registers
To Memory
Dest
from Memory
Dest
Dest
Reservation Stations
2 32R2
4 ROB3
FP adders
FP multipliers
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Relationship between precise interrupts and
speculation

• ??????????
• Branch prediction, data prediction
• If we speculate and are wrong, need to back up
  and restart execution to point at which we
  predicted incorrectly
• This is exactly same as precise exceptions!
• ????????
• Need to take our best shot at predicting branch
  direction.
• If we issue multiple instructions per cycle, lose
  lots of potential instructions otherwise
• Consider 4 instructions per cycle
• If take single cycle to decide on branch, waste
  from 4 - 7 instruction slots!
• ??????????????
• in-order completion or commit
• This is why reorder buffers in all new processors

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??1/2

• Reservations stations ??????,??????
• ?????????
• ???Scoreboard?????? WAR, WAW ??
• ?????????
• ??????(IU??,??????)
• ??
• Dynamic scheduling
• Register renaming
• Load/store disambiguation
• 360/91 ? Pentium II PowerPC 604 MIPS R10000
  HP-PA 8000 Alpha 21264??????

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?? 2/2

• ???????????????????
• ??????????WAR? WAW ??
• Reorder Buffer
• ????????????
• ?????????ROB?
• ??????
• ???????????????
• ????????ROB?????????
• Superscalar ?VLIW CPI lt 1 (IPC gt 1)