CS 61C: Great Ideas in Computer Architecture (Machine Structures) Muxes, Adders, and ALUs

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CS 61C Great Ideas in Computer Architecture
(Machine Structures)Muxes, Adders, and ALUs

• InstructorsRandy H. KatzDavid A. Patterson
• http//inst.eecs.Berkeley.edu/cs61c/fa10

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Agenda

• Multiplexer
• Administrivia
• Technology Break
• ALU Design

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Agenda

• Multiplexer
• Administrivia
• Technology Break
• ALU Design

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Data Multiplexer(e.g., 2-to-1 x n-bit-wide)
mux
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N Instances of 1-bit-Wide Mux
How many rows in TT?
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How Do We Build a 1-bit-Wide Mux?
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4-to-1 Multiplexer
How many rows in TT?
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Alternative Hierarchical Approach
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Arithmetic and Logic Unit

• Most processors contain a special logic block
  called Arithmetic and Logic Unit (ALU)
• Well show you an easy one that does ADD, SUB,
  bitwise AND, bitwise OR

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Simple ALU
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Agenda

• Mutiplexers
• Administrivia
• Technology Break
• ALU

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Agenda

• Mux Adder Design
• Administrivia
• Technology Break
• ALU Design

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Agenda

• Multiplexer
• Administrivia
• Technology Break
• ALU Design

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Adder/Subtractor One-bit adder Least Significant
Bit
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Adder/Subtractor One-bit adder (1/2)
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Adder/Subtractor One-bit Adder (2/2)
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N x 1-bit Adders ? 1 N-bit Adder
Connect Carry Out i-1 to Carry in i
b0
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Overflow Conditions
Add two positive numbers to get a negative
number or two negative numbers to get a positive
number
-1
-1
0
0
-2
-2
1111
0000
1
1111
0000
1
1110
1110
0001
0001
-3
-3
2
2
1101
1101
0010
0010
-4
-4
1100
3
1100
3
0011
0011
-5
-5
1011
1011
0100
4
0100
4
1010
1010
-6
-6
0101
0101
5
5
1001
1001
0110
0110
-7
-7
6
6
1000
0111
1000
0111
-8
-8
7
7
-7 - 2 7!
5 3 -8!
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Overflow Conditions
0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0
1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1
5 3 -8
-7 -2 7
Overflow
Overflow
0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1
1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0
5 2 7
-3 -5 -8
No overflow
No overflow
Overflow when carry in to sign does not equal
carry out Cn xor Cn-1
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Twos Complement Adder/Subtractor
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Design Hierarchy
system
control
datapath
coderegisters
stateregisters
combinationallogic
multiplexer
comparator
register
logic
switchingnetworks
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Summary

• Use muxes to select among input
• S input bits selects 2S inputs
• Each input can be n-bits wide, indep of S
• Can implement muxes hierarchically
• ALU can be implemented using a mux
• Coupled with basic block elements
• N-bit adder-subtractor done using N 1-bit adders
  with XOR gates on input
• XOR serves as conditional inverter