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Computer ArchitectureChapter 3 Instructions

Arithmetic for Computer

Yu-Lun Kuo ??? Department of Computer Science and

Information Engineering Tunghai University,

Taichung, Taiwan R.O.C. sscc6991_at_gmail.com

http//www.csie.ntu.edu.tw/d95037/

Review MIPS Organization

Processor

Memory

11100

src1 addr

src1 data

Register File

5

32

src2 addr

32 registers (zero - ra)

5

dst addr

read/write addr

5

src2 data

write data

230 words

32

32

32

32 bits

branch offset

read data

32

Add

PC

32

32

32

32

Add

32

4

write data

01100

32

01000

32

00100

7

6

5

4

32

00000

ALU

0

1

2

3

32

word address (binary)

32 bits

32

byte address (big Endian)

Memory Address Binding

- High level language ? Machine language?memory

address??????? - ?????
- ?????
- Relocate
- ?????
- Dynamic linking Dynamic loading

Review MIPS Addressing Modes

1. Operand Register addressing

Register

op rs rt rd funct

word operand

R-Type

I-Type

3. Operand Immediate addressing

addi

op rs rt operand

4. Instruction PC-relative addressing

Memory

op rs rt offset

branch destination instruction

Branch

Program Counter (PC)

5. Instruction Pseudo-direct addressing

Memory

op jump address

J-Type

jump destination instruction

Program Counter (PC)

Overview

- Data type includes representation and operations
- lets look at some arithmetic operations
- Addition
- Subtraction
- Sign Extension
- Also look at overflow conditions for addition.
- Multiplication, division, etc.
- Logical operations are also useful
- AND
- OR
- NOT

Signed and Unsigned Numbers

- Humans ? base 10, Computers ? base 2
- Bits are just bits (no inherent meaning)
- Conventions define relationship between bits and

numbers - Binary numbers (base 2) 0000 0001 0010 0011 0100

0101 0110 0111 1000 1001... decimal 0...2n-1 - Of course it gets more complicated
- Numbers are finite (overflow)
- Negative numbers
- e.g., no MIPS subi instruction addi can add a

negative number

Signed and Unsigned Numbers

- Computer program calculate both positive and

negative numbers - Distinguishes the positive from the negative
- Obvious solution
- Add a separate sign
- Conveniently can be represented in a sign bit
- Name of this representation is sign and magnitude

Signed and Unsigned Numbers

- Sign and magnitude representation has several

shortcomings - Not obvious where to put the sign bit
- Right or left?
- Adders may need an extra step to set the sign
- Has both a positive and negative zero
- Lead to problems for inattentive programmers

Signed and Unsigned Numbers

- How do we represent negative numbers?
- i.e., which bit patterns will represent which

numbers? - No use sign and magnitude
- Use twos complement representation
- Leading 0s mean positive
- Leading 1s mean negative
- Twos complement advantage
- All negative numbers have a 1 in the most

significant bit - Hardware needs to test only this bit ( or -)

Signed and Unsigned Numbers

- 32-bit signed numbers (2s complement)0000

0000 0000 0000 0000 0000 0000 0000two 0ten0000

0000 0000 0000 0000 0000 0000 0001two

1ten... - 0111 1111 1111 1111 1111 1111 1111 1110two

2,147,483,646ten0111 1111 1111 1111 1111 1111

1111 1111two 2,147,483,647ten1000 0000 0000

0000 0000 0000 0000 0000two

2,147,483,648ten1000 0000 0000 0000 0000 0000

0000 0001two 2,147,483,647ten... - 1111 1111 1111 1111 1111 1111 1111 1110two

2ten1111 1111 1111 1111 1111 1111 1111 1111two

1ten

(2)10 (0000 0000 0000 0000 0000 0000 0000 0010)2

(1111 1111 1111 1111 1111 1111 1111 1101) 2

(-2)10 (1111 1111 1111 1111 1111 1111 1111

1110) 2

Signed and Unsigned Numbers

- Represent positive and negative numbers
- (x31 x -231)(x30 x 230)(x29 x 229) (x1 x

21)(x0 x 20)

- Converting lt 32-bit values into 32-bit values
- Copy the most significant bit (the sign bit) into

the empty bits - 0010 -gt 0000 0010 1010 -gt 1111 1010 (sign

extend) - sign extend versus zero extend (lb vs.

lbu) - slt vs. slti (set on less than immediate)
- sltu (set on less than unsigned) vs. sltiu

Sign Extension

- To add two numbers, we must represent them with

the same number of bits - If we just pad with zeroes on the left
- Instead, replicate the MS bit -- the sign bit

4-bit 8-bit 0100 (4) 00000100 (still

4) 1100 (-4) 00001100 (12, not -4)

4-bit 8-bit 0100 (4) 00000100 (still

4) 1100 (-4) 11111100 (still -4)

Signed versus Unsigned Comparison

- Suppose register s0 has binary number
- 1111 1111 1111 1111 1111 1111 1111 1111
- Register s1 has the binary number
- 0000 0000 0000 0000 0000 0000 0000 0001
- What are the value of registers t0 and t1
- slt t0, s0, s1 signed
- sltu t1, s0, s1 unsigned
- Ans t0 1 and t1 0

MIPS Arithmetic Logic Unit (ALU)

- Must support the Arithmetic/Logic

operations of the ISA - add, addi, addiu, addu
- sub, subu,
- mult, multu, div, divu
- sqrt
- and, andi, nor, or, ori, xor, xori
- beq, bne, slt, slti, sltiu, sltu

- With special handling for
- sign extend addi, addiu andi, ori, xori, slti,

sltiu - zero extend lbu, addiu, sltiu
- no overflow detected addu, addiu, subu, multu,

divu, sltiu, sltu

Review 2s Complement Representation

2sc binary decimal

1000 -8

1001 -7

1010 -6

1011 -5

1100 -4

1101 -3

1110 -2

1111 -1

0000 0

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

-23

-(23 - 1)

- Negate

23 - 1

A 32-bit Ripple Carry Adder/Subtractor

- Remember 2s complement is just
- complement all the bits
- add a 1 in the least significant bit

A 0111 ? 0111

B - 0110 ?

1001

1

0001

1 0001

Addition Subtraction

- Just like in grade school (carry/borrow 1s)

0111 0111 0110 0110 - 0110 - 0101 - Two's complement operations easy
- subtraction using addition of negative numbers

0111 1010 - Overflow (result too large for finite computer

word) - e.g., adding two n-bit numbers does not yield an

n-bit number 0111 0001 note that overflow

term is somewhat misleading, 1000 it does not

mean a carry overflowed

Overflow

- If operands are too big, then sum cannot be

represented as an n-bit 2s comp number

01000 (8) 11000 (-8) 01001 (9) 10111 (-9)

10001 (-15) 01111 (15)

Overflow Detection

- Overflow
- the result is too large to represent in 32 bits
- Overflow occurs when
- adding two positives yields a negative
- adding two negatives gives a positive
- subtract a negative from a positive gives a

negative - subtract a positive from a negative gives a

positive

1

1

0

0

4

1

0

1

1

3

1

1

6

7

Tailoring the ALU to the MIPS ISA

- Need to support the logic operation

(and,nor,or,xor) - Bit wise operations (no carry operation involved)
- Need a logic gate for each function, mux to

choose the output - Need to support the set-on-less-than instruction

(slt) - Use subtraction to determine if (a b) lt 0

(implies a lt b) - Copy the sign bit into the low order bit of the

result, set remaining result bits to 0 - Need to support test for equality (bne, beq)
- Again use subtraction (a - b) 0 implies a b
- Additional logic to nor all result bits

together - Immediates are sign extended outside the ALU with

wiring (i.e., no logic needed)

Logic Operation ()

- Shift Operations
- Shifts move all the bits in a word left or right
- sll t2, s0, 8 t2 s0 ltlt 8 bits
- srl t2, s0, 8 t2 s0 gtgt 8 bits
- The shift operation is implemented by hardware

separate from the ALU

Logic Operation ()

- sll (R-format)
- Ex. If register s0 is
- 0000 0000 0000 0000 0000 0000 0000 1101
- execute sll s2, s0, 8
- What is the value of s2?
- 0000 0000 0000 0000 0000 1101 0000 0000

sll s2, s0, 8

Arithmetic Logic Unit (ALU)

- Using 4 kinds hardware components

Logical Operations

- Operations on logical TRUE or FALSE
- two states -- takes one bit to represent TRUE1,

FALSE0

A B A OR B

0 0 0

0 1 1

1 0 1

1 1 1

A B A AND B

0 0 0

0 1 0

1 0 0

1 1 1

A NOT A

0 1

1 0

Logic Operation ()

- And (and) instruction
- Or (or) instruction
- Ex. If register t2 is
- 0000 0000 0000 0000 0000 1101 0000 0000
- If register t1 is
- 0000 0000 0000 0000 0011 1100 0000 0000
- Then execute and t0, t1, t2
- The value of t0 is
- 0000 0000 0000 0000 0000 1100 0000 0000

Examples of Logical Operations

- AND
- useful for clearing bits
- AND with zero 0
- AND with one no change
- OR
- useful for setting bits
- OR with zero no change
- OR with one 1
- NOT
- unary operation -- one argument
- flips every bit

11000101 AND 00001111 00000101

11000101 OR 00001111 11001111

NOT 11000101 00111010

Adder (1-bit)

- 1-bit full adder

Adder (4-bit ripple carry adder)

- Each full adder inputs a Cin, which is the Cout

of the previous adder

Adder (32 bit ALU)

- 32-bit adder requires 31 carry computations

Operation

CarryIn

a

Result

b

CarryOut

ALU

- ALU notation

Overflow

Carry out

3.4 Multiplication (1/4)

- Binary multiplication is just a bunch of right

shifts and adds

n

multiplicand

multiplier

partial product array

n

double precision product

2n

Multiplication (2/4)

- More complicated than addition
- accomplished via shifting and addition
- More time and more area
- Ex. Unsigned Multiplication
- (1000)2 x (1011)2

multiplicand

multiplier

Multiplication (3/4)

- The length of the multiplication
- n-bit multiplicand
- m-bit multiplier
- Product is n m bits long
- The n m bits are required to represent all

possible products - We must cope with overflow
- Because we frequently want a 32-bit product as

the result of multiplying two 32-bit numbers

Multiplication (4/4)

- The design mimics the algorithm
- We learned in grammar school
- Assume
- Multiplier in the 32-bit Multiplier register
- 64-bit Product register is initialized to 0
- Write new values into the Product register
- 64-bit Multiplicand register
- Need to move the multiplicand left one digit each

step - Over 32 steps a 32-bit multiplicand would move 32

bits to the left

The First Multiplication Algorithm

- Product register is initialized to 0
- Each step took a clock cycle
- Require almost 100 clock cycle

First Multiply Algorithm (ex. p.180)

- Using 4-bit number to save space
- Multiply 2ten X 3ten (0010 X 0011)

The Second Multiplication Algorithm

- Multiplicand register, ALU, and Multiplier

register are all 32 bits wide - Only Product register is 64 bits (initial 0)
- The multiplier is placed instead in the right

half on the Product register

The Second Multiplication Algorithm

Multiply in MIPS

- MIPS has two instructions
- Multiply mult
- Multiply unsigned multu
- MIPS multiply instructions ignore overflow
- Up to the software to check to see if the product

is too big to fit in 32 bits

3.5 Division

- Division is just a bunch of quotient digit

guesses and left shifts and subtracts

n

quotient

n

0

0

0

dividend

divisor

0

partial remainder array

0

0

remainder

n

Division

- MIPS has two instructions
- Divide div
- Divide unsigned divu
- As with multiply, divide ignores overflow
- Software must determine if the quotient is too

large - Software must also check the divisor to avoid

division by 0

3.6 Floating Point (p.189)

- We need a way to represent
- numbers with fractions, e.g., 3.14159265 (p)
- very small numbers, e.g., .000000001
- very large numbers, e.g., 3.15576 X 109

Floating Point

- Representation
- sign, exponent, significand (1)sign X

significand X 2exponent - more bits for significand gives more accuracy
- more bits for exponent increases range
- IEEE 754 floating point standard
- single precision 8 bit exponent, 23 bit

significand - double precision 11 bit exponent, 52 bit

significand

Representing Big (and Small) Numbers

- What if we want to encode the approx. age of the

earth? - 4,600,000,000 or 4.6 x 109
- or the weight in kg of one a.m.u. (atomic

mass unit) - 0.0000000000000000000000000166 or

1.6 x 10-27

- Floating point representation (-1)sign x F x

2E - Still have to fit everything in 32 bits (single

precision)

Floating Point Form

- Generally of the form
- (-1)S F 2E
- Single precision
- Double precision

1-bit

8-bit

23-bit

Exponent

Significand

S

1-bit

11-bit

20-bit

Significand (continue)

32-bit

Floating Point Form

- Generally of the form
- (-1)S F 2E
- Single precision
- S the sign of the floating-point number
- Exponent the value of the 8-bit exponent field
- Fraction(significand) the 23-bit number
- Sign and magnitude (?????)
- The sign has a separate bit from the rest of the

number

1-bit

8-bit

23-bit

Overflow Underflow

- Overflow
- Means that the positive exponent is too large to

be represented in the exponent field - Underflow
- Means that the negative exponent is too large to

be represented in the exponent field

(No Transcript)

IEEE 754 floating-point standard (1/2)

- These format go beyond MIPS
- They are part of the IEEE 754 floating-point

standard - To pack even more bits into the significand
- IEEE754 makes the leading 1 bit of normalized

binary numbers implicit - The number is 24 bits long in single precision
- Implied 1 and a 23-bit fraction
- The number is 53 bits long in double precision
- Implied 1 and a 52-bit fraction

IEEE 754 floating-point standard (2/2)

- 0 has no leading 1
- It is given the reserved exponent value 0
- 00000two represents 0
- The representation of the rest of the numbers
- (-1)S (1Fraction) 2E
- _at_F is stored in normalized form where the msb in

the fraction is 1 (so there is no need to store

it!) called the hidden bit - _at_ E specifies the value in the exponent field
- If number the bits of the fraction from left to

right s1, s2, s3, - (-1)S(1(s12-1) (s22-2) (s32-3))2E

Signed and Unsigned Numbers

- 32-bit signed numbers (2s complement)0000

0000 0000 0000 0000 0000 0000 0000two 0ten0000

0000 0000 0000 0000 0000 0000 0001two

1ten... - 0111 1111 1111 1111 1111 1111 1111 1110two

2,147,483,646ten0111 1111 1111 1111 1111 1111

1111 1111two 2,147,483,647ten1000 0000 0000

0000 0000 0000 0000 0000two

2,147,483,648ten1000 0000 0000 0000 0000 0000

0000 0001two 2,147,483,647ten... - 1111 1111 1111 1111 1111 1111 1111 1110two

2ten1111 1111 1111 1111 1111 1111 1111 1111two

1ten

(2)10 (0000 0000 0000 0000 0000 0000 0000 0010)2

(1111 1111 1111 1111 1111 1111 1111 1101) 2

(-2)10 (1111 1111 1111 1111 1111 1111 1111

1110) 2

IEEE 754

- The designers of IEEE 754 wanted a floating

point - The sign is in the most significant bit
- Could be easily processed by integer comparisons,

especially for sorting - Quick test of less than, greater than, or equal

to 0 - Negative exponents pose a challenge to simplified

sorting - If we use twos complement in which negative

exponents have a 1 in the MSB - Negative exponent will look like a big number

IEEE 754 Biased Notation (1/2) (p.194)

- Biased notation
- The most negative exponent as 0000two
- The most positive exponent as 1111two
- Bias of 127 for single precision and 1023 for

double precision - ?? E Biased (???)

IEEE 754 Biased Notation (2/2) (p.194)

- IEEE 754 floating point standard
- (-1)sign x (1F) x 2E-bias
- Formats for both single and double precision
- 127 for single and 1023 for double precision
- F is stored in normalized form where the msb in

the fraction is 1 (so there is no need to store

it!) ?called the hidden bit

Floating Point Representation (ex.195)

- Show the IEEE 754 binary representation -0.75

in single precision - -3/4ten ? -3/22ten - ( ½ ¼ ) ? -0.11two
- -0.11two X 20 ? - 1.1two X 2-1
- Sign is 1 number is negative
- Exponent field is 01111110 126 (decimal)
- Fraction is 0.100000000000 0.5 (decimal)
- Value -1.5 x 2(126-127) -1.5 x 2-1 -0.75
- 10111111010000000000000000000000

sign

exponent

fraction

Converting Binary to Decimal FP

- 1 10000001 01000000000000000000000
- The sign bit 1
- The exponent field 129
- The fraction field 12-2 (0.25)
- (-1)sign x (1F) x 2E-bias
- (-1)1 x (10.25) x 2129-127
- -1 x 1.25 x 22
- -1.25 x 4
- -5.0

Floating-Point Addition (p.199)

- Addition (and subtraction) Algorithm on p.200
- (?F1 ? 2E1) (?F2 ? 2E2) ?F3 ? 2E3

- Step 1 Restore the hidden bit in F1 and in F2
- Step 1 Align fractions by right shifting F2 by

E1 - E2 positions (assuming E1 ? E2) keeping

track of (three of) the bits shifted out in a

round bit, a guard bit, and a sticky bit - Step 2 Add the resulting F2 to F1 to form F3
- Step 3 Normalize F3 (so it is in the form

1.XXXXX ) - If F1 and F2 have the same sign ? F3 ?1,4) ? 1

bit right shift F3 and increment E3 - If F1 and F2 have different signs ? F3 may

require many left shifts each time decrementing

E3 - Step 4 Round the sum F3 and possibly normalize

F3 again - Step 5 Rehide the most significant bit of F3

before storing the result

Floating-Point Addition (ex.)

- Adding 0.5ten and -0.4375ten in binary
- 0.5 (0.1)2 (1.000)2 2-1
- -0.4375 - (0.0111)2 - (1.110)2 2-2
- Step 1. Exponent matches the larger number
- - (1.110)2 2-2 - (0.111)2 2-1
- Step 2. Add the significands
- (1.000)2 2-1 - (0.111)2 2-1 (0.001)2 2-1
- Step3. Normalize the sum
- (0.001)2 2-1 (1.000)2 2-4
- Step4. Round the sum
- (1.000)2 2-4 (0.0001000)2 (1/24)10

(1/16)10 (0.0625)10 ANS

- Q A

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