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Title: Direct Digital Frequency Synthesizer (DDFS) ?? ? ??


1
Direct Digital Frequency Synthesizer (DDFS) ?? ?
??
Digital Systems Lab ??? ??
2
? ? (1/2)
  • ?? ?? ? ??
  • Frequency Synthesizer
  • Direct Digital Frequency Synthesizer ??
  • Phase Accumulator
  • Sine Generation Architecture
  • ROM based
  • Taylor Series
  • CORDIC based
  • ROM Compression Method
  • Phase Truncation
  • Quadrant Method
  • Sunderland Algorithm
  • Sine-Phase Difference Algorithm

3
? ? (2/2)
  • VHDL ? ??? DDFS ??
  • Phase Accumulator
  • Coarse Q-ROM
  • Coarse E-ROM
  • Fine Q-ROM
  • Fine E-ROM
  • Phase-to-Sine Conversion Encoder
  • Modified Adder
  • Phase-to-Sine Conversion Decoder
  • Sine Wave Generation
  • DDFS

4
?? ?? ? ??
  • PLL ? ??? ??? ???? ????? ??? (feedback) ??? ???
    ??? ?? ??? ??? ?? ???.
  • DDFS ? ??? ??? ?? ??? ???? ??? ??? ?? ? ????.
  • PLL ??? ????? Voltage-controlled oscillator (VCO)
    ? ?????, DDFS ??? VCO ? ?? ?? ??? VCO? ?? Phase
    noise ? ?? ??.
  • DDFS ??? ?? ??? ??? ???? PLL ????? ??.
  • ROM ? ?? ????? ?? ??? ROM size? ??? ?? DDFS ???
    ????.

5
Frequency Synthesizer
  • ??? ???
  • ?? ?????? ??? ??? ??? ????? ??
  • ??, ????, ???? ?? ??? ???? ???? ???? ??.
  • ??? ????? ?? ??? ???, ?? ??? ???, Direct Digital
    Frequency Synthesizer (DDFS) ? ?? ??? ??? ??? ??
    ??.

6
Direct Digital Frequency Synthesizer ??(1/4)
  • DDFS? ?? ?? ?????

7
Direct Digital Frequency Synthesizer ??(2/4)
  • ?? ??? ?? ??? ??? sine ??? ??? ??? ?? ?? ???? ??
  • DDFS? ??? ??? 4?? ??? ??????.
  • Phase Accumulator (PA)
  • Phase-to-Sine Converter
  • Digital-Analog Converter (DAC)
  • Low Pass Filter (LPF)
  • PA? Phase-to-Sine Converter? Digital part? ???.
  • DAC? LPF? Analog part? ???.

8
Direct Digital Frequency Synthesizer ??(3/4)
  • Phase Accumulator
  • ? clock ?? L ??? Frequency control word (FCW) ?
    Phase Accumulator ? ???? ?? ?? ????.
  • Phase Accumulator ??? ?? FCW ? ????? overflow ??
    ??.
  • Phase Accumulator ? ???? ?? L ??? ? ??? MSB (Most
    Significant Bit) ?? ?? ?? N ??? Phase-to-Sine
    converter ? ????.

9
Direct Digital Frequency Synthesizer ?? (4/4)
  • Phase-to-Sine Converter ? ???? ??
  • ROM table ? ??
  • Taylor series ? ??
  • Coordinated Rotation Digital Computer (CORDIC) ?
    ??
  • ?? ??
  • Phase-to-Sine Converter ? ??? ?? ?? DAC? ????
    ???? ??? ??
  • ????? Low Pass Filter (LPF) ? ???? ??? ???? Sine
    ??? ?? ? ??.

10
DDFS? ?? ???? ???
  • DDFS ? ?? ???
  • ??? ???
  • Phase accumulator ? ?? ? (L) ? ?? clock ???? ??
    ?? ??? ???? ????.

11
Phase Accumulator(1/3)
  • Fc (clock frequency) ? ?? FCW ? phase accumulator
    ? ????? Am? ????.

12
Phase Accumulator(2/3)
  • Phase accumulator? ???? ???? ??
  • 4?? phase accumulator ? ?? ??
  • ???? (Full Adder) 4?? ??? ??? ??
  • Carry ? ??? ?? ?? ?? ??? ?? ???.

13
Phase Accumulator(3/3)
  • Pipeline ? ??? Phase accumulator
  • ?? ???? ?? ?? D-???? ? ????.
  • ???? ??? ??? Pre-skewing ????? De-skewing ????? ??

14
Sine Generation Architecture(1/4)
  • ROM based
  • Sine wave generation?? ?? ?? ?? ???? ROM ?
    look-up ?? ??
  • ?? ?? ROM ? ?? ?
  • ROM ? ??? ??? ?? ??
  • Quadrant method
  • Sunderland Algorithm
  • Sine-phase difference Algorithm

15
Sine Generation Architecture(2/4)
  • ROM based architecture? ??
  • ???? ??? ??.
  • ROM ??? ?? ??, ?? ??? ?? ??? ?????.
  • ROM based architecture? ??
  • ???? ?? ?? ROM ??? ???.
  • ROM ??? ??? ??? ????, ?????? ????.

16
Sine Generation Architecture(3/4)
  • Taylor Series
  • ??? ???? ????, ???? ROM data? look-up??.
  • Taylor series expansion
  • ??
  • ROM based ???? ???? ??.
  • ROM? ??? ?? ??? ???.
  • ??
  • ???? ????.
  • Sine ?? ???? Cosine ?? ?? ROM? ??

17
Sine Generation Architecture(4/4)
  • CORDIC based
  • ROM look-up ??? ???? ??
  • ?? Coordinated Rotation Digital Computer (CORDIC)
    ?? ??
  • ROM ??? ??? ?? ??
  • ??
  • sin, cos ?? ??? ??
  • Pipeline ? ?? ?? ??
  • ??
  • ??? ??
  • ?? ?? ??

18
ROM compression Method(1/12)
  • Phase Truncation
  • ROM ? ??? ??? ??? (N)
  • L Phase Accumulator ? ???
  • K ROM ? ?? ?? ?
  • N ? k ? ?? ??? ???.
  • Phase Truncation
  • Phase accumulator ? ?? ? ? ?? N ??? ???? ??

19
ROM compression Method(2/12)
  • Quadrant method
  • N bit?  FCW ?ø? clock ??? fclk ? ?? ?? ??? ??
  • P bit? Accumulator ??? sine ??? ?????? ROM
    look-up table? Address? ??

20
ROM compression Method(3/12)
  • Minimum frequency resolution
  • Output frequency
  • Quadrant Method
  • sine ??? ???? ??
  • rad sine ???? ???? rad? sine ??? ??

Phase MSB MSB-1 Sine
0ltf lt90 0 0 sinf
90ltf lt180 0 1 sin(90-f )
180ltf lt270 1 0 -sinf
270ltf lt360 1 1 -sin(90-f)
21
ROM compression Method(4/12)
  • Sunderland algorithm
  • Phase ( ) ? ? ???? ??
  • MSB part
  • ?? part
  • LSB part

22
ROM compression Method(5/12)
  • Phase? 0? ?? 90? ??? ???? 12-bit data
  • ?? 4-bit data
  • ROM ? ???? 11-bit data

23
ROM compression Method(6/12)
  • ?? ??? ??
  • ??? ROM ? ??

  • ?? ??? ??
  • ? ???? ???
    coarse ROM ??
  • ? ???? ???
    fine ROM ??

24
ROM compression Method(7/12)
  • ? ?? ? ? ??? ?? ??.
  • ? ?? ?? 7??? ?? 0
    ???
  • ROM ? ??? ??? ???? fine ROM ? ??? 4 ??? ?
  • ?
  • ??? ROM ? ? ?? ?? ROM ?? ?? ??
  • ?? ??? coarse ROM ? fine ROM ? ???? ?? ?
  • ???? ???? ?? ??

25
ROM compression Method(8/12)
  • Sine-phase difference algorithm
  • 0? ?? 90???? ???? Sine ?? ROM ? ???? ?? ?? ?? ??
    ROM ? ??
  • ??? ??? ??? ROM ? ??

26
ROM compression Method(9/12)
  • Sunderland ??? sine-phase difference ?? ??

27
ROM compression Method(10/12)
  • ? ???? ? 0.21 ??? ? ???? ? 5
    ?? 1 ? ??? ROM ? ???? ??.
  • ROM ? ?? ?? ?? 2 ?? ?? ? ??.
  • ROM ???? ? ??? ?? ???? ??? ??
  • Sine-phase difference algorithm ? ?? ?? ????
    Sunderland ????? coarse ROM ? ??? ?? ? ??.
  • Coarse ROM ? Fine ROM ? ?? Quantization ROM
  • (Q-ROM) ? Error ROM (E-ROM)?? ???.
  • E-ROM ? ??? ROM ? Q-ROM ??? error ?? ????.

28
ROM compression Method(11/12)
29
ROM compression Method (12/12)
30
VHDL ? ??? DDFS ??
  • Phase Accumulator
  • Coarse Q-ROM
  • Coarse E-ROM
  • Fine Q-ROM
  • Fine E-ROM
  • Phase-to-Sine conversion Encoder
  • Modified Adder
  • Phase-to-Sine conversion Decoder
  • Sine wave generator
  • DDFS

31
Phase Accumulator ??(1/2)
  • library ieee
  • use ieee.std_logic_1164.all
  • use ieee.std_logic_unsigned.all
  • use ieee.std_logic_arith.all
  • entity phase_accumulator is
  • port (fcw in std_logic_vector (13 downto 0)
  • reset, sclk in std_logic
  • out_addr out std_logic_vector (13 downto 0))
  • end phase_accumulator
  • -- fcw is a 14-bit input data.
  • -- sclk is system clock.
  • -- out_addr is a 14-bit output address data.

32
Phase Accumulator ??(2/2)
  • architecture phase_accumulator of
    phase_accumulator is
  • signal reg std_logic_vector (13 downto 0)
    "00000000000000"
  • -- ???? ???? ?? ?? reg ? ?? ? ???
  • begin
  • process (reset, sclk)
  • begin
  • if reset1' then -- reset
  • reg lt "00000000000000"
  • elsif sclk'event and sclk'1' then
  • -- clock ??? rising edge ? ? event ??
  • end if
  • end process
  • end phase_accumulator

--reg? fcw?? ??
-- ??? ?? ??
33
Phase Accumulator RTL view
34
Phase Accumulator simulation
35
Coarse Q-ROM ??(1/2)
  • library ieee
  • use ieee.std_logic_1164.all
  • entity cqrom is
  • port (addr in std_logic_vector (5 downto 0)
  • data out std_logic_vector (5 downto
    0))
  • end cqrom
  • architecture cqrom of cqrom is
  • constant x_state std_logic_vector "XXXXXX"
  • -- data is a 6-bit output data. (CQ9 ? CQ4)

36
Coarse Q-ROM ??(2/2)
  • begin
  • process (addr)
  • begin
  • case addr is
  • when "000000" gt data lt "000000"
  • when "000001" gt data lt "000010"
  • .
  • .
  • when "111111" gt data lt "000000"
  • when othersgt data lt x_state
  • end case
  • end process
  • end cqrom

37
Coarse Q-ROM simulation
38
Coarse E-ROM ??(1/2)
  • library ieee
  • use ieee.std_logic_1164.all
  • entity cerom is
  • port (addr in std_logic_vector (7 downto 0)
  • data out std_logic_vector (4 downto 0))
  • end cerom
  • architecture cerom of cerom is
  • constant x_state std_logic_vector "XXXXX"
  • -- data is a 5-bit output data. (CE5 ? CE1)

39
Coarse E-ROM ??(2/2)
  • begin
  • process (addr)
  • begin
  • case addr is
  • when "00000000" gt data lt "00000"
  • when "00000001" gt data lt "00100"
  • .
  • .
  • when "11111111" gt data lt "00111"
  • when others gt data lt x_state
  • end case
  • end process
  • end cerom

40
Coarse E-ROM simulation
41
Fine Q-ROM ??(1/2)
  • library ieee
  • use ieee.std_logic_1164.all
  • entity fqrom is
  • port (addr in std_logic_vector (4 downto 0)
  • data out std_logic_vector (1 downto 0))
  • end fqrom
  • architecture fqrom of fqrom is
  • constant x_state std_logic_vector "XX"
  • -- data is a 2-bit output data. (FQ3 ? FQ2)

42
Fine Q-ROM ??(2/2)
  • begin
  • process (addr)
  • begin
  • case addr is
  • when "00000" gt data lt "00"
  • when "00001" gt data lt "11"
  • .
  • .
  • when "11111" gt data lt "00"
  • when others gt data lt x_state
  • end case
  • end process
  • end fqrom

43
Fine Q-ROM simulation
44
Fine E-ROM ??(1/2)
  • library ieee
  • use ieee.std_logic_1164.all
  • entity ferom is
  • port (addr in std_logic_vector (7 downto 0)
  • data out std_logic_vector (2 downto 0))
  • end ferom
  • architecture ferom of ferom is
  • constant x_state std_logic_vector "XXX"
  • -- data is a 3-bit output data. (FE3 ? FE1)

45
Fine E-ROM ??(2/2)
  • begin
  • process (addr)
  • begin
  • case addr is
  • when "00000000" gt data lt "000"
  • when "00000001" gt data lt "000"
  • .
  • .
  • when "11111111" gt data lt "000"
  • when others gt data lt x_state
  • end case
  • end process
  • end ferom

46
Fine E-ROM simulation
47
Phase-to-Sine Conversion Encoder ??(1/2)
  • library ieee
  • use ieee.std_logic_1164.all
  • use ieee.std_logic_unsigned.all
  • entity sc_encoder is
  • port (addr in std_logic_vector (13 downto 0)
  • -- phase accumulator ? ?? ?? ?? ??? ??
  • cq out std_logic_vector (5 downto 0)
  • ce out std_logic_vector (7 downto 0)
  • fq out std_logic_vector (4 downto 0)
  • fe out std_logic_vector (7 downto 0)
    -- ? ROM ? ??? ?? data
  • sphase out std_logic_vector (7 downto
    0) -- Sine-phase difference
  • msb out std_logic) -- ?? address?
    ??? ??
  • end sc_encoder
  • architecture sc_encoder of sc_encoder is
  • begin

48
Phase-to-Sine Conversion Encoder ??(2/2)
  • process (addr)
  • begin
  • if addr (12)'0' then -- sine ? ??
  • elsif addr(12)'1' then -- sine ? ??
  • end if
  • end process
  • end sc_encoder

-- sine ? ??? ROM address mapping
-- sine ? ??? ROM address mapping
-- address? ? ?? bit? ???
49
Phase-to-Sine Conversion Encoder simulation
50
Modified Adder ??(1/3)
  • library ieee
  • use ieee.std_logic_1164.all
  • use ieee.std_logic_unsigned.all
  • entity madder is
  • port (cq in std_logic_vector (5 downto 0)
  • ce in std_logic_vector (4 downto 0)
  • fq in std_logic_vector (1 downto 0)
  • fe in std_logic_vector (2 downto 0) --
    ? ROM ? ???
  • sphase in std_logic_vector (7 downto
    0) -- Sine-phase difference
  • qsinout out std_logic_vector (10 downto
    0))
  • -- ? ROM? ???? sine-phase
    difference ?? ?
  • end madder
  • architecture madder of madder is
  • begin
  • end madder

-- ?ROM? ???? ???
51
Modified Adder ??(2/3)
52
Modified Adder ??(3/3)
53
Modified Adder simulation
54
Phase-to-Sine Conversion decoder ??
  • library ieee
  • use ieee.std_logic_1164.all
  • entity sc_decoder is
  • port (qsin in std_logic_vector (10 downto 0)
  • -- modified adder ? ???
  • sign in std_logic -- encoder ??? ??? msb
  • sinout out std_logic_vector (11 downto 0))
  • -- ?? ?? sine ?
  • end sc_decoder
  • architecture sc_decoder of sc_decoder is
  • begin
  • end sc_decoder

-- modified adder? ???? sign?? ???
55
Phase-to-Sine Conversion decoder simulation
56
Sine wave generator ??(1/5)
  • library ieee
  • use ieee.std_logic_1164.all
  • entity sin_gen is
  • port (addr in std_logic_vector (13 downto 0)
    -- 14-bit ?? address
  • sinout out std_logic_vector (11 downto
    0)) -- 12-bit ?? sine ?
  • end sin_gen
  • architecture sin_gen of sin_gen is
  • component sc_encoder
  • end component

-- component ??
57
Sine wave generator ??(2/5)
  • component cqrom
  • end component
  • component cerom
  • end component
  • component fqrom
  • end component
  • component ferom
  • end component

-- component ??
-- component ??
-- component ??
-- component ??
58
Sine wave generator ??(3/5)
  • component madder
  • end component
  • component sc_decoder
  • end component

-- component ??
-- component ??
59
Sine wave generator ??(4/5)
  • signal cq_in std_logic_vector (5 downto 0)
  • signal ce_in std_logic_vector (7 downto 0)
  • signal fq_in std_logic_vector (4 downto 0)
  • signal fe_in std_logic_vector (7 downto 0)
  • signal cq_out std_logic_vector (5 downto 0)
  • signal ce_out std_logic_vector (4 downto 0)
  • signal fq_out std_logic_vector (1 downto 0)
  • signal fe_out std_logic_vector (2 downto 0)
  • signal sphase std_logic_vector (7 downto 0)
  • signal sign std_logic
  • signal sum std_logic_vector (10 downto 0)

60
Sine wave generator ??(5/5)
  • begin
  • end sin_gen

-- port mapping
61
Sine wave generator RTL view
62
Sine wave generator simulation(1/2)
63
Sine wave generator simulation(2/2)
64
DDFS ??(1/2)
  • library ieee
  • use ieee.std_logic_1164.all
  • entity ddfs is
  • port (fcw in std_logic_vector (13 downto 0)
  • reset, sclk in std_logic
  • sinout out std_logic_vector (11 downto
    0))
  • end ddfs
  • -- 14-bit frequency control word ? ????? ???
  • -- 12-bit sine data? ??
  • architecture behave of ddfs is
  • component phase_accumulator
  • end component

-- port ??
65
DDFS ??(2/2)
  • component sin_gen
  • end component
  • signal addr_temp std_logic_vector (13 downto
    0)
  • begin
  • end behave

-- port ??
-- port mapping
66
DDFS RTL view
67
DDFS simulation
68
????
  • Jinchoul Lee, Hyunchul Shin, "New Effective ROM
    Compression Methods for ROM-based Direct Digital
    Frequency Synthesizer Design, IEICE Trans.
    Communications, Nov. 2004 , pp.3352-3355
  • ???, ???, "New ROM Compression Methods for Direct
    Digital Frequency Synthesizers", 2002 SOC Design
    Conference ???? ???, Oct. 2002
  • J.Tierney,C.M. Rader, and B. Gold, "A digital
    frequency synthesizer", IEEE Trans. Audio
    Electroacoustic, vol. AU-19, pp. 48-56, mar.
    1971.
  • David A Sunderland, et al., "CMOS/SOS Frequency
    Synthesizer LSI Circuit for Spread Spectrum
    Communications", IEEE J. Solid-State Circuits,
    vol. 19, no. 4, pp. 497-505, Aug. 1984.
  • ByungDo Yang, KiHyuk Sung, YoungJoon Kim, Lee-Sup
    Kim, Seon-Ho Han, and HyunKyu Yoo, A Direct
    Digital Frequency Synthesizer Using A New ROM
    Compression Method, European Solid-State Circuit
    Conference 2001, Sep. 2001.
  • L.A. Weaver, 'High Resolution Phase to Sine
    Amplitude Conversion',U.S. Patent 4 905 177, Feb.
    1990.
  • Minkyoung PARK, "CORDIC-Based Direct Digital
    Frequency Synthesizer  Comparison with a
    ROM-Based Architecture in FPGA Implementation", 
    IEICE Trans. FUNDAMENTAL, Vol. E83-A, No. 6, pp.
    1282-1285, June 2000.
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