RS-232 Port

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RS-232 Port

• Discussion D12.1

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RS-232 voltage levels 5.5 V (logic 0) -5.5 V
(logic 1)
Loop feedback
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PC DTE female connector
Spartan-3 board DCE male connector
Straight-through cable
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Note TxD (pin 2) on Spartan-3 DCE connector is
connected to RD (pin 2) on the PC DTE
connector
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UART clock frequency 16 x Baud rate or 64 x
Baud rate
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Standard ASCII Codes
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How would you make the following hardware Tx UART?
8-bit parallel data comes in tx_data(70) and is
loaded into a transmit buffer txbuff when tdre is
high. When ready goes high the contents of txbuff
is sent out TxD as asynchronous serial data.
When txbuff is empty, tdre is set to 1.
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UART Transmit State Diagram
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VHDLCanonical Sequential Network
init
Combinational Network
s(t1)
s(t)
State Register
next state
present state
x(t)
present input
process(clk, init)
present output
clk
z(t)
process(present_state, x)
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VHDLMealy Machine
process(present_state, x)
init
C1
C2
s(t1)
State Register
next state
s(t)
z(t)
present state
x(t)
present input
process(present_state, x)
clk
process(clk, init)
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VHDLMoore Machine
init
C2
C1
z(t)
s(t1)
State Register
next state
s(t)
present state
x(t)
present input
process(present_state, x)
process(present_state)
clk
process(clk, init)
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VHDLCanonical Sequential Network
init
Combinational Network
s(t1)
s(t)
State Register
next state
present state
x(t)
Combine into a single process
present input
process(clk, init)
present output
clk
z(t)
process(present_state, x)
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UART Transmit State Diagram
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entity uart_tx is port( clk in
STD_LOGIC clr in STD_LOGIC tx_data in
STD_LOGIC_VECTOR(7 downto 0) ready in
STD_LOGIC tdre out STD_LOGIC TxD out
STD_LOGIC ) end uart_tx
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architecture uart_tx of uart_tx is type
state_type is (mark, start, delay, shift,
stop) signal state state_type signal txbuff
STD_LOGIC_VECTOR (7 downto 0) signal baud_count
STD_LOGIC_VECTOR (11 downto 0) signal bit_count
STD_LOGIC_VECTOR (3 downto 0) constant bit_time
STD_LOGIC_VECTOR (11 downto 0) X"A28" begin
9600 baud
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uart2 process(clk, clr, ready) begin if
clr '1' then state lt mark txbuff lt
"00000000" baud_count lt X"000" bit_count lt
"0000" TxD lt '1' elsif (clk'event and clk
'1') then case state is when mark
gt -- wait for ready bit_count lt
"0000" tdre lt '1' if ready '0'
then state lt mark
txbuff lt tx_data else baud_count
lt X"000" state lt start --
go to start end if
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when start gt -- output start bit baud_count
lt X"000" TxD lt '0' tdre lt '0'
state lt delay -- go to delay when delay
gt -- wait bit time tdre lt '0' if
baud_count gt bit_time then baud_count lt
X"000" if bit_count lt 8 then -- if not
done state lt shift -- go to shift
else -- else state lt stop --
go to stop end if else baud_count lt
baud_count 1 state lt delay --
stay in delay end if
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when shift gt -- get next bit tdre lt
'0' TxD lt txbuff(0) txbuff(6
downto 0) lt txbuff(7 downto 1) bit_count lt
bit_count 1 state lt delay when stop
gt -- stop bit tdre lt'0' TxD lt '1'
if baud_count gt bit_time then
baud_count lt X"000" state lt mark
else baud_count lt baud_count 1
state lt stop end if
end case end if end process uart2
end uart_tx
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Test Transmit UART
Set slide switches to some ASCII code and then
press button 0 to send ASCII code out serial port.
SW
BTN(0)
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entity tx_tst_ctrl is port( clk in
STD_LOGIC clr in STD_LOGIC btn in
STD_LOGIC tdre in STD_LOGIC ready out
STD_LOGIC ) end tx_tst_ctrl
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architecture tx_tst_ctrl of tx_tst_ctrl is type
state_type is (wtbtndn, wttdre, load,
wtbtnup) signal state state_type begin ctrl
process(clk, clr, btn, tdre) begin if clr
'1' then state lt wtbtndn ready lt '0'
elsif (clk'event and clk '1') then case
state is when wtbtndn gt -- wait for
btn if btn '0' then -- if bnt up
state lt wtbtndn -- stay in wtbtndo
ready lt '0' else ready lt '0'
state lt wttdre -- else go to
wttdre end if
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when wttdre gt -- wait for tdre 1 if tdre
'0' then -- if tdre 0 state lt
wttdre -- stay in wtdone ready lt '0'
else state lt load -- else go to
load ready lt '0' end if when load
gt -- output ready ready lt '1'
state lt wtbtnup -- go to wtbtnup
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when wtbtnup gt -- wait for btn up if
btn '1' then -- if btn down state
lt wtbtnup -- stay in wtbtnup ready lt
'0' else ready lt '0'
state lt wtbtndn -- else go to wtbtndn
end if end case end if
end process ctrl end tx_tst_ctrl
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Test Transmit UART Top-level design
entity uart_tx_test is port ( mclk in
STD_LOGIC sw in STD_LOGIC_VECTOR(7 downto
0) btn in STD_LOGIC_VECTOR(3 downto 0)
ld out STD_LOGIC_VECTOR(7 downto 0) TxD
out STD_LOGIC ) end uart_tx_test
Pin "R13"
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architecture uart_tx_test_arch of uart_tx_test is
component uart_tx port( clk in
STD_LOGIC clr in STD_LOGIC tx_data in
STD_LOGIC_VECTOR(7 downto 0) ready in
STD_LOGIC tdre out STD_LOGIC TxD out
STD_LOGIC ) end component component
tx_tst_ctrl port( clk in STD_LOGIC
clr in STD_LOGIC btn in STD_LOGIC
tdre in STD_LOGIC ready out STD_LOGIC
) end component
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component debounce4 port( clk in
std_logic clr in std_logic inp in
std_logic_vector(3 downto 0) outp out
std_logic_vector(3 downto 0)) end
component signal clr, clk, cclk
std_logic signal tdre, ready std_logic signal
clkdiv std_logic_vector(23 downto 0) signal
btnd std_logic_vector(3 downto 0) begin
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-- Divide the master clock (50Mhz) down to a
lower frequency. process (mclk) begin if clr
'1' then clkdiv lt "000000000000000000000000"
elsif mclk '1' and mclk'Event then
clkdiv lt clkdiv 1 end if end
process clk lt clkdiv(0) -- 25 MHz cclk lt
clkdiv(17) -- 190 Hz ld(7) lt btnd(1)
ld(6) lt btnd(2) ld(5) lt btnd(1) ld(4) lt
btnd(2) ld(3) lt btnd(1) ld(2) lt btnd(2)
ld(1) lt btnd(1) ld(0) lt tdre clr lt
btnd(3)
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U1 uart_tx port map (TxD gt TxD, clk gt clk,
clr gt clr, ready gt ready, tx_data gt sw,
tdre gt tdre) U2 tx_tst_ctrl port map (clk
gt clk, clr gt clr, btn gt btnd(0), tdre gt tdre,
ready gt ready) U3 debounce4 port
map( clk gt cclk, clr gt clr, inp gt
btn, outp gt btnd ) end uart_tx_test_arch
btn(0)
sw
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How would you make the following hardware Rx UART?
8-bit asynchronous serial data comes in RxD and
fills up the shift register data_rx. When
data_rx is full, rdrf is set to 1. rdrf is
cleared to zero by bringing clrflg high. The
framing error flag FE is set to 1 if the stop bit
is not 1.
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UART Receive State Diagram
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entity uart_rx is port( RxD in
STD_LOGIC clk in STD_LOGIC clr in
STD_LOGIC rdrf_clr in STD_LOGIC rdrf
out STD_LOGIC FE out STD_LOGIC rx_data
out STD_LOGIC_VECTOR(7 downto 0) ) end
uart_rx
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architecture uart_rx of uart_rx is type
state_type is (mark, start, delay, shift,
stop) signal state state_type signal rxbuff
STD_LOGIC_VECTOR (7 downto 0) signal baud_count
STD_LOGIC_VECTOR (11 downto 0) signal bit_count
STD_LOGIC_VECTOR (3 downto 0) signal rdrf_set,
fe_set, cclr, cclr8, rxload STD_LOGIC constant
bit_time STD_LOGIC_VECTOR (11 downto 0)
X"A28" constant half_bit_time STD_LOGIC_VECTOR
(11 downto 0) X"514" begin
9600 baud
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uart2 process(clk, clr, rdrf_clr) begin
if clr '1' then state lt mark rxbuff lt
"00000000" baud_count lt X"000" bit_count lt
"0000" FE lt '0' elsif rdrf_clr '1'
then rdrf lt '0' elsif (clk'event and clk
'1') then case state is when mark
gt -- wait for start bit baud_count lt
X"000" bit_count lt "0000" if
RxD '1' then state lt mark
else FE lt '0'
state lt start -- go to start
end if
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when start gt -- check for start bit
if baud_count gt half_bit_time then
baud_count lt X"000" state lt
delay else baud_count lt baud_count
1 state lt start end
if when delay gt if
baud_count gt bit_time then baud_count lt
X"000" if bit_count lt 8 then state lt
shift else state lt
stop end if else baud_count lt
baud_count 1 state lt delay
end if
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when shift gt -- get next bit rxbuff(7)
lt RxD rxbuff(6 downto 0) lt rxbuff(7 downto
1) bit_count lt bit_count 1 state lt
delay when stop gt rdrf lt
'1' if RxD '0' then FE lt
'1' else FE lt '0'
end if state lt mark end case
end if end process uart2 rx_data lt
rxbuff end uart_rx
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Test of UART
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Test Receive UART
Receive ASCII code sent from terminal program on
PC when key is pressed and display on LEDs.
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Test Transmit UART
Echo back ASCII code sent from PC.
rdrf_clr
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entity test2_rx_ctrl is port( clk in
STD_LOGIC clr in STD_LOGIC rdrf in
STD_LOGIC rdrf_clr out STD_LOGIC
) end test2_rx_ctrl
architecture test2_rx_ctrl of test2_rx_ctrl
is type state_type is (wtrdrf, load) signal
state state_type
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begin ctrl process(clk, clr, rdrf) begin
if clr '1' then state lt wtrdrf rdrf_clr
lt '0' elsif (clk'event and clk '1')
then case state is when wtrdrf
gt rdrf_clr lt '0' if rdrf '0'
then state lt wtrdrf
else state lt load
end if when load
gt rdrf_clr lt '1' state lt
wtrdrf end case end if
end process ctrl end test2_rx_ctrl
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Top-level test of UART
entity uart_test2 is port ( mclk in
STD_LOGIC BTN3 in STD_LOGIC RxD in
STD_LOGIC LD out STD_LOGIC_VECTOR(7 downto
0) TxD out STD_LOGIC ) end
uart_test2 architecture uart_test2_arch of
uart_test2 is component uart_tx port(
clk in STD_LOGIC clr in STD_LOGIC
tx_data in STD_LOGIC_VECTOR(7 downto 0)
ready in STD_LOGIC tdre out STD_LOGIC
TxD out STD_LOGIC ) end component
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component tx_tst_ctrl port( clk in
STD_LOGIC clr in STD_LOGIC btn in
STD_LOGIC tdre in STD_LOGIC ready out
STD_LOGIC ) end component component
uart_rx port( RxD in STD_LOGIC clk
in STD_LOGIC clr in STD_LOGIC rdrf_clr
in STD_LOGIC rdrf out STD_LOGIC FE
out STD_LOGIC rx_data out
STD_LOGIC_VECTOR(7 downto 0) ) end
component
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component test2_rx_ctrl port( clk in
STD_LOGIC clr in STD_LOGIC rdrf in
STD_LOGIC rdrf_clr out STD_LOGIC
) end component signal clr, clk, cclk
std_logic signal tdre, rdrf, rdrf_clr, FE,
ready, btn std_logic signal clkdiv
std_logic_vector(23 downto 0) signal data
std_logic_vector(7 downto 0)
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begin -- Divide the master clock (50Mhz) down
to a lower frequency. process (mclk) begin if
clr '1' then clkdiv lt "000000000000000000000
000" elsif mclk '1' and mclk'Event then
clkdiv lt clkdiv 1 end if end
process clk lt clkdiv(0) -- 25 MHz cclk lt
clkdiv(17) -- 190 Hz LD lt data clr
lt BTN3 btn lt rdrf_clr
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U1 uart_tx port map (TxD gt TxD, clk gt clk,
clr gt clr, ready gt ready, tx_data gt
data,tdre gt tdre) U2 uart_rx port map
(RxD gt RxD, clk gt clk, clr gt clr, rdrf_clr gt
rdrf_clr, rx_data gt data,rdrf gt rdrf, FE gt
FE) U3 tx_tst_ctrl port map (clk gt clk,
clr gt clr, tdre gt tdre, btn gt btn, ready gt
ready) U4 test2_rx_ctrl port map (clk gt
clk, clr gt clr, rdrf gt rdrf, rdrf_clr gt
rdrf_clr) end uart_test2_arch