Low Power Implementation of Scan Flip-Flops - PowerPoint PPT Presentation

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Low Power Implementation of Scan Flip-Flops

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Title: Serial ATA Technology Author: Chris Erickson Last modified by: Christopher Created Date: 9/14/2006 6:30:17 PM Document presentation format – PowerPoint PPT presentation

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Title: Low Power Implementation of Scan Flip-Flops


1
Low Power Implementation of Scan Flip-Flops
Chris Erickson Graduate Student Department of
Electrical and Computer Engineering Auburn
University, Auburn, AL 36849 Chris.Erickson_at_auburn
.edu
2
Objectives
  • Scan flip-flop overview
  • Ways to incorporate low power design
  • Benchmark circuit
  • Results

3
Scan Flip-Flop
Primary outputs
Primary inputs
Combinational logic
Scan-out SO
Scan flip- flops
D
D
SO
D
0 1
Scan enable SE
DFF
mux
D
SI
Scan-in SI
SE
4
How does is work?
Primary inputs
Primary outputs
Combinational logic
Scan-out 100
FF0 FF0 FF1
Scan-in 010
5
Low Power Scan Flip-Flop
SO
D
DFF
D
mux
SI
SE
Scan FF cell
6
Validation of lpsff
  • Q grounds upon entering scan-mode
  • QS provides output to scan chain

7
Benchmark Circuit
  • S5378
  • 35 Inputs
  • 49 Outputs
  • Standard
  • 179 D-type flip-flops
  • 1775 Inverters
  • 239 Or gates
  • 765 Nor gates
  • Flattened/optimized
  • Scan FF
  • 967 complex gates
  • Low-Power Scan FF
  • 1152 complex gates

8
Test Patterns
Primary Input Patterns
  • 55 h
  • AA h
  • All 1s
  • All 0s
  • Random but constant 1
  • Random but constant 2
  • All Random

9
Gate Transitions
AAh
All 0
55h
All 1
Rand 2
Rand 1
All
Rand
10
Gate Events
AAh
All 0
55h
All 1
Rand 2
Rand 1
All
Rand
11
Average Power Consumption (uW)
AAh
All 0
55h
All 1
Rand 2
Rand 1
All
Rand
12
Power Reduction
sff ? lpsff
55 h 35.1
AA h 22.8
All 1 22.9
All 0 33.0
Random 1 (const) 23.9
Random 2 (const) 18.8
All Random 0
Only encountered if entering into scan mode and
the system didnt know to latch the input signals.
13
Conclusion
  • Low Power Scan Chain can result in up to 35
    power reduction.
  • Minimal 19 area overhead from standard scan
    chain flip-flop
  • Average power reduction of 20-30 if input
    signals are held static

14
References
  • TSMC 0.25um process parameters
  • Mentor Graphics Leonardo for design synthesis
  • Auburns PowerSim3 used for power measurements
    Created by Jins Alexander
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