EE141 Project Phase 3

1
EE141 Project Phase 3
Name 1, Name 2

• Key Results
• Worst case process corner
• Sense amp offset voltage
• Worst case propagation delay
• Nominal case propagation delay

2
Poster Instructions

• Fill the content of previous cover slide
• Replace this and later slides with your own
  materials
• Since the poster board is 30x40, limit the
  number of slides to 12 (including the cover
  slide)
• While poster board and mounting tools (glue,
  knife, ruler, etc.) will be provided at BWRC, you
  are responsible for printing the slides
  beforehand and for mounting them onto the board
• BWRC will be open for poster preparation on
  Wednesday (5/6) 1200 pm.

3
Directions to BWRC

• http//bwrc.eecs.berkeley.edu/Background/direction
  s.htm

4
Key Content

• Critical path identified
• Circuit topology and analysis
• Logic gate sizing
• Considerations for worst-case process variation
• Sense amplifier sizing and offset voltage
• Key waveforms.

5
Poster Session Format

• Both team members are expected present during the
  time slot signed up
• Each team will be given 10 minutes to present
  the work and 35 minutes for QA
• Grade will be based on completeness and accuracy
  of results, as well as quality of presentation.

6
Last but not least

• Remember to email your slides to
  ee141_at_cory.eecs.berkeley.edu
• by Wednesday (5/6) 1200 pm!