FPGA Defect Tolerance: Impact of Granularity

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FPGA Defect Tolerance Impact of Granularity

• Anthony Yu Guy Lemieux
• December 14, 2005

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Outline

• Introduction and motivation
• Previous works
• New architectures
• Coarse-grain redundancy (CGR)
• Fine-grain redundancy (FGR)
• Experimentation Results
• Conclusions

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Introduction and Motivation

• Scaling introduces new types of defects
• Smaller feature sizes susceptible to smaller
  defects
• Expected results
• Defects per chip increases
• Chip yield declines
• FPGAs are mostly interconnect
• FPGAs must tolerate multiple interconnect defects
  to improve yield (and )

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General Defect Tolerant Techniques

• Defect-tolerant techniques minimize impact (cost)
  of manufacturing defects
• FPGA defect-tolerance can be loosely categorized
  into three classes
• Software Redundancy use CAD tools to map around
  the defects
• Hardware Redundancy incorporate spare resources
  to assist in defect correction (eg. Spare
  row/column)
• Run-time Redundancy protection against
  transient faults such as SEUs (eg. TMR)

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Previous work 1 Xilinx

• Xilinxs Defect-Tolerant Approach
• Customer (knowingly) purchases less that
  perfect parts
• Customer gives Xilinx configuration bitstream
• Xilinx tests FPGA devices against bitstream
• Sells FPGA parts that appear perfect
• Defects avoid the bitstream
• Limitation
• Chips work only with given bitstream no changes!

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Previous work 2 Altera

• Alteras Defect-Tolerant Approach
• Customer purchases seemingly perfect parts
• Make defective resources inaccessible to user
• Coarse-grain architecture
• Spare row and column in array (like memories)
• Defective row/column must be bypassed
• Use the spare row/column instead
• Limitation
• Does not scale well (multiple defects)

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Objective

• Problem
• FPGA yield is on decline because of aggressive
  technology scaling
• Proposed Solutions
• Defect-tolerance through redundancy
• Important Objectives
• Interconnect defects important (dominates area)
• Tolerate multiple defects (future trend)
• Preserve timing (no timing re-verification)
• Fast correction time (production use)
• Understand the factors that influence yield

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Background
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Island-style FPGA
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Directional Switch Block
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Directional Switch Block
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Course-grain Redundancy (CGR)
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Coarse-grain Redundancy (CGR)
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Sowhats wrong with it?
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Improving yield for CGR Adding Multiple Global
Spares

• Add multiple global spare to traditional CGR
• Global spares can be used to repair any defective
  row/column in the array
• Wire extensions are now longer

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Yield Impact of Multiple Global Spares
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Increasing AreaDelay Overhead
MORE SPARES ? MORE MUX OVERHEAD IN EVERY SWITCH
ELEMENT
NO SPARES
2 GLOBAL SPARES
4 GLOBAL SPARES MAY BE IMPRACTICAL !!!
1 GLOBAL SPARE
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Improving yield for CGR Adding Multiple Local
Spares

• Divide FPGA into subdivisions
• Each subdivision has local spare(s)
• Distributes spares across chip
• Reduces mux area overhead(of Global scheme)
• Limitation
• Spare(s) can only repair defect within the
  subdivision

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Yield Impact of Multiple Local Spares(not as
good as Global with same spares)
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Fine-grain Redundancy (FGR)
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Fine-grain Redundancy (FGR) Defect Avoidance by
Shifting
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Defect-tolerant Switch Block
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Switch Implementation Options

• Several detailed implementations are possible
• Trade off area / delay / yield(repairability)

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Minimum Fault-free Radius (MFFR)
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Experimentation Results

• Switch implementation
• Array size
• Wire length
• Area
• Summary

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Switch Implementation
Assumes all bridging defects
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Fixed Array Size (32x32) Global Sparing
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Fixed Array Size (32x32) Local Sparing
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Increasing Array Size
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Yield for Varying Wire Length
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Estimated Area overhead at equal yield (80)
CGR-G1 can only tolerate 1-2 defects
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Limitations of Study Architectures

• Logic and power/ground shorts were not considered
• Assumed that all defects are randomly distributed
• Assumed that all defects can be corrected with a
  single row/column
• Switch area was not accounted for our yield model
• Area results for CGR are approximated

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Conclusions

• CGR is effective for 1 or 2 defects
• FGR meets desired objectives
• Tolerates multiple randomly distributed defects
• Defect correction does not perturb timing
• Tolerates an increasing number of defects as
  array size increases
• Correction can be applied quickly

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Thank you!

• anthonyy_at_ece.ubc.ca

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Summary

• As the density of FPGAs increase, they becoming
  in susceptible to manufacturing defects
• Fault-redundant techniques alleviate this growing
  problem
• Depending on the desired level of protection, we
  can apply different techniques
• At low defect rates, the spare row and column
  approach has lower overhead than the fine-grain
  approach
• At large array sizes, the spare row and column
  approach requires more area overhead to tolerate
  the same number of defects as the fine-grain
  approach