Before The Production Comes The Design Semiconductors are the physical representation of a logic (software) function

1
Before The Production Comes The
DesignSemiconductors are the physical
representation of a logic (software) function

• Fabricating semiconductors is converting software
  into a physical circuit

e.g. Compress 64Kbps audio stream to 6.7Kbps (GSM
phone)
Algorithm / Software
Design
Mask set
Source Deutsche Bank
2
The Overall Semiconductor Manufacturing Process

• Two major steps 1) front-end (wafer fab) 2)
  back-end (assembly test)

Wafer Fabrication/Front End
Mask Mfg.
Material Management Process Automation
Diffusion/ Implant/ Metal
Wafer Mfg.
Epi - taxy
Photo- resist
Photo- lithography
Etch
Strip
CMP
Inspection Measurement
Test, Assembly Packaging/Back End
Materials Management
Die Bond
Encap- sulation
Test Burn-in
Wafer Test
Wire Bond
Dicing
Source Infrastructure
3
Making Silicon Wafers

• A seed crystal of ultra-pure silicon is suspended
  in a bath of molten silicon
• The crystal is slowly pulled up and grows into a
  cylindrical ingot of pure silicon
• The ingot is ground down to a uniform diameter
  cylinder (200mm/300mm ...)
• The end is cut off, then thin silicon wafers are
  sawn off (sliced) and polished
• The polished wafers are shipped to the
  semiconductor manufacturer to begin the front-end
  process
• Silicon wafers are ultra flat
• analogy if 300mm wafer corresponds to the
  earths equator, flatness 10 metres

Source Deutsche Bank
4
The Front-End Process
Bare Wafer

• Output is an array of semiconductor die
  (individual semiconductor devices) on a
  semiconductor wafer
• A batch process each wafer contains multiple
  (1-10M) die
• A repetitive process but with different materials
  (conductor, insulator, semiconductor) patterns
  (the design)
• Cleaning, inspection and diagnostics occur after
  almost every process step

i) Film Deposition
Wafer with Deposited Layer
The Patterning Process
ii) Lithography/Masking
Wafer with Temporary Resist Pattern
20-30x
Cleaning, Inspection, Diagnostics Automation
iii) Etch
Wafer with Permanently Patterned Layer
iv) Implant/Diffusion
Wafer with Altered Electrical Properties
Finished Wafer
Source Deutsche Bank
5
The Principal Of Front-End ProcessingPatterning
stacked layers

• A semiconductor device consists of patterned and
  stacked electronic materials - 20-30 layers
• semiconductor active transistor
• conductor electrical interconnection of
  independent transistors
• insulator electrical isolation of different
  interconnections dielectric
• Each patterning step corresponds to a different
  mask

Conductor
Insulator
Active transistor
The Different Stacked Layers
The Different Patterning Steps
Source Deutsche Bank, In-Circuit Engineering
6
The Patterning ProcessLithography Etch
Film
Wafer

• Lithography provides a temporary pattern (stepper
  / scanner)
• Etch makes the temporary pattern permanent

Lithography
1. Photoresist Application Spin coat a thin layer
of photoresist on surface
Mask
2. Alignment and Exposure Precise alignment of
mask/reticle to wafer and exposure of photoresist
3. Development Removal of unpolymerised resist
Etch
4. Etch Top layer of wafer is removed through
opening in resist layer
5. Photoresist Removal Remove remaining
photoresist layer from water
Source Deutsche Bank
7
The Lithography Process An extremely high
resolution printing process

• Several process steps
• photoresist application apply photosensitive
  material
• layer alignment pattern exposure
• align current layer to previous layer (accurate,
  high-speed)
• expose wafer surface to light through a patterned
  mask (reticle) - changes chemical properties of
  exposed photoresist
• development removed exposed photoresist areas
  through immersing entire wafer in solvent
• Lithography driven by
• smaller wavelengths of exposing light
• higher numerical aperture lenses - concentrate
  light waves
• other factors - tricks! (optical proximity
  correction - OPC phase-shift masks - PSM ...)

8
The Etch Process

• Removes unwanted material from top surface of
  wafer (normally in areas where photoresist has
  been removed)
• Creates a permanent pattern in surface layer
  material (in insulator, conductor, semiconductor)
• Process can be
• dry gas/plasma, higher precision, expensive
• wet liquid (acid), low precision, inexpensive
• Dry etch is most common and involves charged gas
  plasma bombarding wafer surface - mix of physical
  chemical reaction

9
The Implant / Diffusion Processes

• Alter the electrical properties of the
  semiconductor
• introduce electrical charges (/-), as impurities
  (boron, phosphorus, arsenic), to the
  semiconductor
• normally relates to transistor wells (source
  drain)
• Implant
• implant impurities into the semiconductor
• high-energy, low-temperature process (charges
  bombard wafer surface)
• fine control of charge level and depth
• Diffusion
• diffuse impurities uniformly into the
  semiconductor
• high temperature process (furnace tube) -
  850-1150C
• sometimes proceeded by finely controlled ion
  implant - pre-deposition step

ion implant
diffusion
Source Deutsche Bank
10
Planarisation

• As device structures become smaller and the
  number of patterning layers increases, the wafer
  surface becomes increasingly irregular
• A flat wafer surface is essential to high
  resolution and uniform patterning (during the
  photolithography process) - must planarise the
  wafer surface beforehand
• Traditionally planarisation was achieved with a
  blanket etch process
• Chemical mechanical polishing (CMP) is a physical
  and chemical polishing process which achieves
  more uniform planarisation than blanket etch
• CMP will become increasingly important with the
  advent of damascene copper processing

Patterning on a non-planar surface
Patterning on a planar surface
Source Deutsche Bank
11
The Cleaning Inspection/Diagnostic Processes

• Cleaning
• continuous throughout process
• remove unwanted by-product / intermediate
  materials (photoresist post-etch, etch /
  deposition by-products)
• can be wet (ultra-pure water, chemical), dry
  (plasma) or wet/dry process
• Inspection ( process testing)
• continuous throughout process
• ensure process quality (contamination, electrical
  parameters, feature sizes ...)
• multiple inspection types (reticle, wafer,
  metrology, defects, parametric )
• multiple inspection equipment (microscope,
  pattern inspection, scanning electron microscope
  ...)

Source Deutsche Bank
12
The Back-End Process

• Individual working die are identified and sorted
  from the finished wafer
• The semiconductor die are put into a package

Sawing
Lead Frame
From Front-End
Separate wafer into individual dice
Assembly and Die Attach
Die
Wire Bonding
Molding
Attach die mechanically to lead frame
Attach die electrically to leadframe
Encapsulate die
Forming
Tin Plating
Trimming
Tin plate pins to improve conductivity prevent
corrosion
Bend leadframe pins
Remove unnecessary part of leadframe
Source Deutsche Bank
13
The Semiconductor Package

• The semiconductor package protects the active die
  from the external environment (contamination,
  humidity, temperature ...)
• The package can be an important determinant of
  device performance
• Package technology is accelerating due to
  system-on-chip and handheld product trends
  (smaller size, higher integration ...) -
  package-to-die ratio from 301 to 1.11

Elements Of Semiconductor Package
Typical Semiconductor Packages
Thin Outline Package
Plastic Small Outline Transistor
Small Outline Package
Dual-In-Line Package
Plastic Pin Grid Array
Plastic Leaded Chip Carrier
Plastic Quad Flatpack
Ball Grid Array (BGA)
Chipscale Package (CSP)
Source National Semiconductor
14
Final Test

• Semiconductors are tested throughout the entire
  manufacturing process
• process problems must be identified immediately
• continued processing of defective product is an
  expensive waste of time
• wafer-level testing
• Final test ensures specified product performance
  and quality prior to final customer shipment
• simulates actual operating environment of
  customers target application
• product is 100 tested (electrical, quality,
  speed ...)
• die-level testing
• Main categories of testers parametric, logic,
  memory, mixed signal
• Memory chips can be repaired (laser repair) due
  to built-in redundancy

15
Improving Economics Smaller Die Size (Die
Shrink)

• Employ lithography to create smaller feature
  sizes
• Die size to linewidth relationship is a
  square-function
• This is Moores Law in practice - 15 per annum
• On-track till at least 2007/8 (optical
  lithography)

0.5x
0.5 micron Resolution 100 Die Per Wafer
0.25 micron Resolution 400 Die Per Wafer
4x
Source Deutsche Bank
16
Improving Economics Wafer Size Increase

• Larger wafers provide lower unit costs
• Transition from 200mm to 300mm has (theoretical)
  2.25x area increase
• Investments increase 1.5x
• Upgrade to larger wafer size equipment only
  feasible when whole infrastructure (equipment,
  wafers, automation) is sufficiently mature
• Wafer size transitions have historically taken
  8-9 years

100mm
125mm
150mm
200mm
Relative Die Cost
300mm
Wafer Diameter (mm)
Source Deutsche Bank, In-Circuit Engineering
17
Improving Economics Yield

• Yield relates to the number of good die on each
  wafer - can vary from 30-95
• Yield can be impacted by
• contamination
• defective processing
• Retaining high yields requires cleanroom
  environment and process control (materials,
  parameters ...)
• For same process/product, yields generally
  improve over time - experience curve

High Contamination
Low Contamination
Low Yield
High Yield
Source Deutsche Bank
18
Moores Law Drives The Semiconductor Industry

• The number of transistors on a chip doubles every
  18-24 months
• . requiring 15 linewidth reduction every year

10G
4 Gb
1 Gb
1G
256 Mb
Memory (DRAM)
Pentium IV
64 Mb
100M
16 Mb
PIII
10M
4 Mb
PII
1 Mb
Pentium
1M
Transistors / chip
256 Kb
80386
80486,680
64 Kb
68020
100K
16 Kb
80286
4 Kb
Microprocessor
68000
8086
10K
8085
8080
4004
1K
1970
1975
1980
1985
1990
1995
2000
2005
Source In-Circuit Engineering
19
New equipment, new materials, new processes
1G
DRAM generation (bits)
4G
16G
64G
1T
256G
400
560
790
1120
1580
2240
Chip Size DRAM (mm²)

0.18 0.13
0.10 0.070
0.050 0.035
Dense lines/ DRAM (µm)
0.14 0.10
0.070 0.050
0.035 0.025
Isolated lines/ MPU (µm)
6.2M 18M
39M 84M
180M 390M
Transistors/ cm² (MPU)
340 430
520 620
750 900
Chip Size MPU (mm²)
450mm
450mm
300mm
300mm
300mm
200mm
Wafer Diameter
Mask Count (min)
22 23 24
26 28
gt 28
Metal Layers (Logic)
5-6 6-7 7
7 - 8 8 - 9
9-10
Chip to Board Speed (MHz)
480 785 885
1035 1285
1540 - 1200 -1400 -1600
- 2000 - 2500
- 3000
1998 2000 2002
2004 2006 2008 2010
2012 2014
Year of First Sample Shipment
Source International Technology Roadmap for
Semiconductors
20
Next Generation Lithography (NGL)Enabling the
continuation of Moores Law

• Traditional optical lithography is expected to
  reach limits by 2007/8E (circa 0.05/0.07 micron)
  - 193nm, 157nm, (126nm)
• Industry must find new technologies in order to
  continue to enable Moores Law
• Of four alternatives, EUV has strongest prospects
  - EUV LLC, prototype system, scalability
• Major EUV challenges relate to reflective optics
  and reticles

Next Generation Lithography
Source Deutsche Bank
21
Silicon-on-Insulator (SOI)Driving higher
performance and lower power consumption

• Traditional transistors leak electrical current
  to the silicon substrate, adversely impacting
  speed, power consumption and reliability
  (parasitic junction capacitance)
• An oxide insulating layer (silicon-on-insulator)
  below the gate structure reduces leakage to the
  substrate silicon
• SOI offers important advantages over epitaxial
  polysilicon, depending on the application
• datacomm 20-50 speed
• mobile comms -35 power consumption
• Automotive higher reliability/temperature
• general circuit packing density 20
• Several alternative processes SmartCut (SOITEC),
  SIMOX, SPIMOX, BESOI, ELTRAN

Oxide
Silicon
Silicon
Parasitic capacitance
Standard CMOS
Silicon-on-Insulator
Source IBM Microelectronics
22
Copper/Low-K DielectricTo enhance IC performance
Microprocessor Yesterday 0.35 micron

• As the number of transistors on a chip increases,
  so does the number of interconnects (conduction
  paths) between transistors
• A increased number of interconnects can slow down
  signal propagation, therefore device speed
• Copper is poised to take over as the main on-chip
  conductor for all types of ICs - aluminum
  technology has reached its limits
• lower resistance means faster signal propagation
  (gt 1GHz operation)
• lower capacitance means thinner copper lines -
  lower power consumption and tight packing density
• superior resistance to metal electromigration -
  higher reliability devices
• simplified manufacturing process (-20 cost)
• Copper is being used in conjunction with low K
  dielectrics (reduce interconnect RC delay, metal
  coupling and power consumption)
• Copper patterning requires the implementation of
  an entirely new manufacturing technique
  (damascene) - deposition/planarisation versus
  deposition/etch

Microprocessor Today 0.25-0.18 micron
Microprocessor Tomorrow 0.13-0.10 micron
Source Deutsche Bank
23
Compound Semiconductors Gallium Arsenide /
Silicon GermaniumGoing beyond the capabilities
of silicon

• Silicon is mainstream - low cost but performance
  is limited
• Compound semiconductors are types of
  semiconductor material other than silicon - most
  common are gallium arsenide (GaAs) silicon
  germanium (SiGe)
• Applications include radio frequency devices,
  LEDs, laser diodes
• GaAs is a key semiconductor material for
  high-frequency (mobile comms radio section, data
  comms ...) and photonic (laser diodes,
  photodetectors) applications
• SiGe is a composite material between silicon and
  GaAs
• high-frequency, low-power operation
• compatible with traditional silicon processing
  (BiCMOS) - will probably cannibalise both Si
  GaAs

Source CommQuest, Deutsche Bank