Title: HIGH%20SPEED%20CMOS%20ANALOG-TO-DIGITAL%20CONVERTER
1HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER
CIRCUIT FOR RADIO FREQUENCY SIGNAL
Kyusun Choi
Computer Science and Engineering Department
The Pennsylvania State University
2Goal
Core Development and Silicon Test of 6-bit and
8-bit TIQ Based Flash ADC
- High speed circuit and layout design
- Prototype chip fabrication
- Test and evaluate, explore and improve
3Plan
- Design 6 bit and 8 bit TIQ based ADC circuits and
CMOS layouts - Fabrication of prototype chip in 0.25 ?m CMOS
logic technology - Test prototype chip, extract parameters
- Redesign 6 bit and 8 bit TIQ based ADC circuits
and CMOS layouts - Fabrication of prototype chip in 0.25 ?m or 0.18
?m technology - Test prototype chip, evaluate and improve
4Milestones
- 1st Chip design, synthesis 12/01/2000
- Chip fabrication 02/05/2001
- Chip testing 04/06/2001 1st report
- 2nd chip design, synthesis 06/08/2001 2nd
report, chip - Chip fabrication 08/10/2001
- Chip testing 10/12/2001 3rd report
- Project presentation 11/30/2001 Final report,
chip
5High speed ADC applications
- Wideband RF, baseband RF, and IF signal
- digitization
- Wireless point to point system
- Local multi-point distribution service
- Wireless local loop
- Computer network, universal adaptor
- Radar/communications
6TIQ based ADC
- Flash ADC
- TIQ Threshold Inverter Quantization
- Comparator
- Inverter comparator
7Flash ADC
V1
Vref
Vin
R
V2
V1
R
D1
D2
V3
V2
D3
R
V3
Dk
R
Vn
Vn
Thermometer code to binary encoder
Resistor ladder circuit
8TIQ based ADC
9TIQ Comparator
DIFFERENTIAL INPUT VOLTAGE COMPARATOR
INVERTER
Vr is provided by a voltage references
source, External to the voltage comparator
Vm is an internal parameter of an inverter, fixed
by the transistor sizes
10Advantages of TIQ based ADC
- High speed
- Less area
- No resistor ladder and reference voltages
- No capacitor switching
- Future ready
- Scale down
- Low supply voltage
- Standard digital logic technology
- Ideal for SOC
11Intels 70-nm process takes gate to 30-nm length
Manufacturing is slated for 2005
Process name P858 P860 P1262 P1264
Production 1999 2001 2003 2005
Generation 0.18 0.13 0.10 0.07 ?m
Gate length 0.13 0.07 0.05 0.03 ?m
? Source EE TIMES 12/11/2000
12Challenges of TIQ based ADC
- Process parameter variation
- Single ended input
13Simulation results
- 6bit at 1000 MSPS
- 8bit at 500 MSPS
- Layout area
- Power
- Process parameter variation
14Layout 6-bit TIQ ADC
156-bit 1 GS/s
168-bit 500 MS/s
17Simulation results
Resolution 6-bit 8-bit
CMOS Technology 0.25 ?m 0.25 ?m
Power Supply 2.5 V 2.5 V
ADC Speed 1 GSPS 500 MSPS
ADC Area 0.013 mm2 0.075 mm2
Max Power Consumption 66.87 mW 225.8 mW
Vm Range 0.82 V 0.84 V
18Process variation
Process Name Start Vm End Vm Vm Range Avg. Distance Max. Power Avg. Power
n94s 0.6815V 1.4999V 0.8184V 0.0132V 66.87mW 44.35mW
n99w 0.6911V 1.5030V 0.8119V 0.0131V 64.53mW 40.46mW
n99y 0.6819v 1.4808V 0.7989V 0.0129V 65.97mW 41.57mW
n9bm 0.6984V 1.4983V 0.7999V 0.0129V 65.30mW 41.70mW
t02b 0.6874V 1.5288V 0.8414V 0.0136V 72.29mW 46.51mW
t02d 0.6955V 1.5188V 0.8233V 0.0133V 71.48mW 45.29mW
19Innovation challenges
- 2 GSPS with 0.18um CMOS
- Custom layout CAD tool
- 10bit and 12bit ADC
- Low power
- Dynamic calibration
- Offset
- Gain
- Temperature
- Power supply voltage
- Process parameter variation
20Summary
- High speed ADC for RF
- ADC core - 6bit and 8bit design
- prototype chips (silicon test)
- 0.25 ?m (or 0.18 ?m)
- CMOS digital logic technology
- Future ready
- Dynamic calibration