Camera Electronics

1
Camera Electronics - John Oliver -

• Contributors to Camera Electronics conceptual
  design 2003-2006
• BNL Veljko Radeka, Paul OConnor
• Harvard John Oliver, Christopher Stubbs
• Harvard Smithsonian CfA John Geary
• Discussions presentations at Camera and
  All-Hands meetings

• Additional current contributors to Camera
  Electronics
• U. Penn (FEB)
• OSU (Fiber optics)
• ORNL/U. Tennessee (Sensor Control Chip)
• Brandeis (Timing Control Module)
• LAL/LPNHE Paris (ASPIC chip)

2
Critical specs and decisions
Read noise 5 e rms
Read time 2 sec
FPA size 3,200 MPixels
Full well 105 electrons
Xtalk 0.01
3
Critical specs and decisions
Read noise 5 e rms
Read time 2 sec
FPA size 3,200 MPixels
Preamps in cryostat as close as possible to
sensors
Full well 105 electrons
Short sensor to preamp cables
Xtalk 0.01
4
Camera conceptual models BEE in or out of
cryostat
Cryostat
Sensors
FEE
FEB/BEB connections
BEE
Data fibers
Timing Control
Ethernet setup Command
Power conversion
Mains
5
Decision time BEE in or out?

• FEB to BEB connections 24 differential analog,
  power ,bias, control
• 120 pins per FEB/BEB combination (redundant
  power pins)
• 6 FEB/BEB pairs per crate ? 720 pins per crate
• 25 crates ? 18,000 pins

6
Decision time BEE in or out?

• Concern about massive feedthrough count
• Judgment that additional pcb area in cryostat
  could be made contamination free with suitable
  materials (polyimide) and coatings (Parylene)
• Strict attention to contamination issue in
  Camera design materials certification

• BEE in cryostat
• 30 conductor feedthroughs per Raft
• 600 total
• Shortest FEB/BEB cables
• 2x pcb area

7
Additional features of baseline design

• Separation of functionality
• Front End
• Analog only
• - 100C thermal zone
• Back End
• ADCs, digital only, housekeeping, data
  formatting, data fiber output
• - 40C thermal zone
• ASIC based analog functions (Sensor Control
  Chip, ASPIC)
• Differential signaling only on interconnects
  LVDS, differential analog
• Single timing source Timing Control module
  (outside cryostat)
• Fully synchronous readout All rafts do the
  same thing at the same time
• Flexible and fully configurable Readout State
  Machine (FPGA based)
• Robust grounding no ground loops within camera
• To outside world (CCS, DAQ) camera appears as
• Ethernet addresses for setup and high level
  command (eg READ)
• Mains power input
• Data fibers to DAQ

8
Questions

• Signal buffering on Sensor packages
• Double source follower, single source follower,
  or external fet Under discussion with vendors
• Critical spec is output impedance lt 1kW
• Need low time constant on cable
• Thermal control loop on sensor packages
• Temp sensor on package
• Heater resistors on package or thermal straps
• Target /- 1C absolute, /- 0.1C stability
• Heater dissipation 0.25 to 0.5 W per sensor
  (biased at midpoint)
• Electronics prototype effort
• Low channel count discrete prototypes
  (Harvard/Penn) ? Demonstrated 1.8 ADC count
  pedestal width
• ASIC/ADC prototype (LAL/LPNHE) ? Demonstrated
  electronic xtalk 0.007 , Noise performance
  close but problem understood in simulations
  (1/f problem)
• Full channel count BEE, partial channel count FEE
  ASIC based in progress
• Raft tower, Raft Control Crate mechanical designs
  done, thermal models in progress

9
Questions

• Contamination
• Polyimide pcb technology
• Parylene coating
• SLAC materials certification facility
• Synchronization
• Each Raft Control Module (in RCC) is synched to a
  single common Timing Control Module with a
  single master clock (50 MHz)
• Full synchronicity across focal plane to several
  nanoseconds skew, and sub-nanosecond jitter.
• Xtalk
• Measured electronic crosstalk 0.007 from ASPIC
  through data output interface
• Will be dominated by sensor to preamp cable (high
  density design).
• Modeling, designing, and testing of this cable
  interface is a critical item.
• Power distribution, filtering, static protection
• Power delivered separately to all rafts
• Power sequencing envisioned for supplies in
  Utility Trunk
• Filtering, bypassing, and sub-regulation done at
  all links in the chain.

10
Questions

• Electronic failures
• Failure rate of silicon devices expected to be
  exceedingly low at reduced temperatures.
• Connector pins are expected to dominate ? These
  have been chosen exceedingly conservatively
• Redundant pins when possible
• Possible failure scenarios
• Single channel (segment)
• Single half sensor (top or bottom row of 8)
• Single sensor
• Row of three sensors
• Entire raft
• Diagnostics in place at many levels of the chain
• Repair scenario
• Modular construction
• Replace faulty crate (Raft Tower or Raft Control
  Crate)
• Service faulty crate/card/connector/cable in
  service facility and recertify for future use.

11
Questions

• Power dissipation heat removal
• Radiated power through lens ½ W per sensor
• FEE electronic power 1.5 W per sensor
• BEE electronic power 2 W peak, per sensor
• Note Idle mode available on both FEBs, and
  BEBs. Potential for substantial power savings
  active during READ only.
• Turn-on times for Idle Mode for BEBs have been
  measured and are small ( mseconds)
• All heat removal is through conduction
• Chip scale packages where available
• Heavy thermal planes
• Heat transmitted to crate
• Taken out by cryoplate (Raft Tower) and coldplate
  (Raft Control Crate)
• Thermal models used during design and updated as
  necessary