A Simplified, Cost-Effective MPLS Labeling Architecture for Access Networks

1
A Simplified, Cost-Effective MPLS Labeling
Architecture for Access Networks

• Harald Widiger1, Stephan Kubisch1, Daniel
  Duchow1, Thomas Bahls2, Dirk Timmermann1
• 1University of Rostock, Germany
• 2Siemens Communications, Greifswald, Germany

2
Outline

• Access Network Architecture
• Multi Protocol Label Switching
• The MPLS-User Network Interface
• Implementation and Simulation Results
• Conclusion

3
Access Network Environment

• Need for Differential Services, increased QoS
• Derived from Information within each Frame
• MPLS-UNI to create space for information

4
Multi Protocol Label Switching (MPLS)

• Encapsulation Scheme
• Meant for fast routing purposes
• Here Simply a container to carry information

• Path of a Frame through an MPLS switched Network

5
MPLS-Encapsulation

• MPLS Label Stack usually between layer 2 and
  layer 3 header
• We use encapsulation scheme by Martini

6
MPLS-User Network Interface (MPLS-UNI)

• MPLS Label Stack container to carry information
• No complete LER implementation with an LDP
  running is necessary
• Possibility to implement the whole system in
  Hardware
• Primary Functionality
• Upstream direction ?insert an MPLS Label Stack
• Downstream direction ? remove MPLS Label Stacks

7
MPLS-UNI Architecture
8
Framebuffer with Key Parser

• Stores frames and parsed keys
• Key is configurable at time of compilation
• Reduction of required hardware resources in the
  MPLS-UNI itself

9
Memory Arbitration
10
Implementation Results(Xilinx Virtex 4 FX20-11)
Hardware Module Hardware Module Speed in MHz Area Area
Hardware Module Hardware Module Speed in MHz Logic min/typ/max BRAMs
MPLS-UNI MPLS-UNI 1125/1486/2227 11/11/12
MPLS-Labeler 187 129 2
MPLS-Delabeler 322 101 0
Memory Arbiter 163 152/203/343 0
CPU Arbiter 168 640 0
Key Parser Framebuffer 159 352/494/721 9/9/10
Framebuffer 177 205 0
Memory internal (1K Entries) Memory internal (1K Entries) 126 783/1145/1917 3/7/15
Sync FIFOs MACs Sync FIFOs MACs 169 850 6
?System ?System 130 2600/3400/4700 20/24/33
11
Performance

• 4 Gbps _at_ natural Traffic
• 30 60 Byte
• 10 590 Byte
• 11 1514 Byte
• 49 random
• No packet loss
• Average delay of 120 Cycles ? 860 ns _at_125 MHz

12
Conclusion

• Powerful and cost-effective solution to expand
  MPLS networks into the Access Network area
• _at_125 MHz, 4 Gbps can be handled
• Size of the system can be minimized considering
  the actual tasks
• Functional spectrum can be broadened, due to
  reconfigurable HW