Transition Delay Fault Testing of Microprocessors by Spectral Method

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Transition Delay Fault Testing of Microprocessors
by Spectral Method

• Nitin Yogi and Vishwani D. Agrawal
• Auburn University
• Department of ECE
• Auburn, AL 36849, USA

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Outline

• Introduction
• Defects and transition delay fault model
• Microprocessor testing Issues
• Problem and Approach
• Register-transfer level modeling of transition
  delay faults
• Spectral analysis and test generation
• Design for Testability
• Experimental Results
• Conclusion

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An Open Circuit Defect
Reference W. Maly, Realistic Fault Modeling for
VLSI Testing, Proceedings of the 24th ACM/IEEE
Design Automation Conference, 1987, Miami Beach,
Florida, Pages 173-180.
4
A Bridging Defect
Reference W. Maly, Realistic Fault Modeling for
VLSI Testing, Proceedings of the 24th ACM/IEEE
Design Automation Conference, 1987, Miami Beach,
Florida, Pages 173-180.
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A Possible Delay Defect
Reference W. Maly, Realistic Fault Modeling for
VLSI Testing, Proceedings of the 24th ACM/IEEE
Design Automation Conference, 1987, Miami Beach,
Florida, Pages 173-180.
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Stuck-at Fault Model
Fault activated
Stuck-at 0
A
Fault detected
B
Y
C
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Transition (Delay) Fault Model
Fault activated
Slow-to-rise fault
A
Fault detected
B
Y
C
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Microprocessor Testing Issues

• Issues arising from Increased Design Complexity
• Increased Demands on Testing
• A Viable Test Method Functional at-speed tests
• Advantages easy to derive cover many defects
• Disadvantages Long test sequences full coverage
  not guaranteed
• Need Fault-Oriented Test Generation Methods
• Test pattern generators work at gate level
• Have very high complexity
• RTL Test Generation
• Advantages
• Low testing complexity
• Early detection of testability issues

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Problem and Approach

• The problem is
• Develop an RTL ATPG method to generate functional
  at-speed tests.
• And our approach is
• Circuit characterization using RTL
• RTL test generation
• Analysis of information content and noise in RTL
  vectors.
• Test generation for gate-level implementation
• Generation of spectral vectors
• Fault simulation and vector compaction

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Faults Modeled at Register-Transfer Level
CombinationalLogic
Inputs
Outputs
RTL modules
RTL transition delay fault sites
FF
FF
A circuit is an interconnect of several RTL
modules.
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Analyzing Bit-Streams of RTL Tests
Input 1 Input 2 . . .
Vector 1 Vector 2 . . .
Bit-stream
0 to -1
Bit-stream of Input 2
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Spectral Characterization of a Bit-Stream
Bit stream to analyze
Correlating with Walsh functions by multiplying
with Hadamard matrix.
Bit stream
Spectral coeffs.
Essential component (others regarded noise)
Hadamard Matrix H(3)
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Generation of New Bit-Streams
Perturbation
Spectral components
Generation of new bit-stream by multiplying with
Hadamard matrix
Essential component retained noise components
randomly perturbed
New bit stream
Sign function
-1 to 0
Bits changed
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PARWAN Processor
Reference Z. Navabi, Analysis and Modeling of
Digital Systems. New York McGraw-Hill, 1993.
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Power Spectrum for Interrupt Bit-Stream
Analysis of 128 test vectors.
Essential components
Some noise components
Normalized Power
Randomlevel(1/128)
Spectral Coefficients
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Power Spectrum for DataIn5 Signal
Analysis of 128 test vectors.
Some essential components
Some noise components
Normalized Power
Theoretical random noiselevel(1/128)
Spectral Coefficients
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RTL Design for Testability (DFT)

• Goals of DFT
• Improve fault coverage
• Most hard-to-detect transition faults were
  experimentally found to have poor observability
• XOR tree as DFT
• Low area overhead
• Low performance penalty
• Hard-to-detect RTL faults used for observation
  test points
• 24 observation test points selected

XOR tree
To test output
Hard-to-detect RTL transition faults
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Experimental Results
RTL transition fault characterization
PARWAN processor
No of RTL Transition Faults No. of vectors CPU (s) RTL coverage () Gate-level fault coverage()
737 160 3652 77.07 47.84
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Experimental Results
ATPG used Version of PARWAN circuit CPU secs. No. of vectors Stuck-at fault cov. () Transition fault cov. ()
RTL-spectral for transition faults Original 6428 6700 97.60 81.85
RTL-spectral for transition faults DFT for t-f 6428 5120 98.25 85.94
RTL-spectral combined stuck-at transition tests Original 9027 98.47 81.85
RTL-spectral combined stuck-at transition tests DFT for s-a-f 7086 98.91 85.87
RTL-spectral combined stuck-at transition tests DFT for t-f 7086 98.77 86.27
Gate-level FlexTest for transition faults Original 43574 1318 92.44 73.79
Gate-level FlexTest for transition faults DFT for t-f 40119 1444 96.29 81.90
Random vectors Original 51200 82.28 58.67
Random vectors DFT for s-a-f 51200 86.20 65.82
Sun Ultra 5, 256MB RAM
N. Yogi and V. D. Agrawal, Spectral RTL Test
Generation for Microprocessors, in Proc. 20th
International Conf. VLSI Design, Jan. 2007, pp.
473-478.
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Experimental Results
Stuck-at Vectors
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Experimental Results
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Conclusion

• Spectral RTL ATPG technique applied to PARWAN
  processor for transition delay faults.
• Proposed ATPG method provides
• Good quality almost functional at-speed
  transition delay tests
• Lower test generation complexity
• Enables testability appraisal at RTL
• RTL based XOR tree as DFT improved fault
  coverage.
• Test optimization for multiple fault models
• Yogi and Agrawal, Optimizing Tests for Multiple
  Fault Models, submitted to the North Atlantic
  Test Workshop 2007.

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• Thank You !
• Questions ?