361 Computer Architecture Lecture 12: Designing a Pipeline Processor

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361Computer ArchitectureLecture 12 Designing a
Pipeline Processor
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Overview of a Multiple Cycle Implementation

• The root of the single cycle processors
  problems
• The cycle time has to be long enough for the
  slowest instruction
• Solution
• Break the instruction into smaller steps
• Execute each step (instead of the entire
  instruction) in one cycle
• Cycle time time it takes to execute the longest
  step
• Keep all the steps to have similar length
• This is the essence of the multiple cycle
  processor
• The advantages of the multiple cycle processor
• Cycle time is much shorter
• Different instructions take different number of
  cycles to complete
• Load takes five cycles
• Jump only takes three cycles
• Allows a functional unit to be used more than
  once per instruction

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Multiple Cycle Processor

• MCP A functional unit to be used more than once
  per instruction

PCWr
PCWrCond
PCSrc
BrWr
Zero
ALUSelA
MemWr
IRWr
RegWr
RegDst
IorD
1
Mux
32
PC
0
32
Zero
Rs
Ra
RAdr
5
32
32
Rt
Rb
busA
32
Ideal Memory
32
Instruction Reg
Reg File
5
32
4
Rt
0
32
Rw
WrAdr
32
1
32
Rd
Din
Dout
busW
32
busB
2
32
3
Imm
32
ALUOp
MemtoReg
ExtOp
ALUSelB
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Outline of Todays Lecture

• Recap and Introduction
• Introduction to the Concept of Pipelined
  Processor
• Pipelined Datapath and Pipelined Control
• How to Avoid Race Condition in a Pipeline Design?
  
• Pipeline Example Instructions Interaction
• Summary

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Pipelining is Natural!

• Laundry Example
• Sammy, Marc, Griffy, Alberteach have one load of
  clothes to wash, dry, and fold
• Washer takes 30 minutes
• Dryer takes 30 minutes
• Folder takes 30 minutes
• Stasher takes 30 minutesto put clothes into
  drawers

A
B
C
D
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Sequential Laundry
2 AM
6 PM
12
8
1
7
10
11
9
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
T a s k O r d e r
Time

• Sequential laundry takes 8 hours for 4 loads
• If they learned pipelining, how long would
  laundry take?

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Pipelined Laundry Start work ASAP
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2 AM
6 PM
8
1
7
10
11
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Time
T a s k O r d e r

• Pipelined laundry takes 3.5 hours for 4 loads!

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Pipelining Lessons

• Pipelining doesnt help latency of single task,
  it helps throughput of entire workload
• Multiple tasks operating simultaneously using
  different resources
• Potential speedup Number pipe stages
• Pipeline rate limited by slowest pipeline stage
• Unbalanced lengths of pipe stages reduces speedup
• Time to fill pipeline and time to drain it
  reduces speedup
• Stall for Dependences

6 PM
7
8
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Time
T a s k O r d e r
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Why Pipeline?

• Suppose we execute 100 instructions
• Single Cycle Machine
• 45 ns/cycle x 1 CPI x 100 inst 4500 ns
• Multicycle Machine
• 10 ns/cycle x 4.6 CPI (due to inst mix) x 100
  inst 4600 ns
• Ideal pipelined machine
• 10 ns/cycle x (1 CPI x 100 inst 4 cycle drain)
  1040 ns

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Timing Diagram of a Load Instruction
Instruction Fetch
Instr Decode /
Address
Reg Wr
Data Memory
Reg. Fetch
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
ExtOp
Old Value
New Value
ALUSrc
Old Value
New Value
RegWr
Old Value
New Value
Register File Access Time
busA
Old Value
New Value
Delay through Extender Mux
Register File Write Time
busB
Old Value
New Value
ALU Delay
Address
Old Value
New Value
Data Memory Access Time
busW
Old Value
New
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The Five Stages of Load
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Load

• Ifetch Instruction Fetch
• Fetch the instruction from the Instruction Memory
• Reg/Dec Registers Fetch and Instruction Decode
• Exec Calculate the memory address
• Mem Read the data from the Data Memory
• Wr Write the data back to the register file

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Pipelining the Load Instruction
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Clock
2nd lw
3rd lw

• The five independent functional units in the
  pipeline datapath are
• Instruction Memory for the Ifetch stage
• Register Files Read ports (bus A and busB) for
  the Reg/Dec stage
• ALU for the Exec stage
• Data Memory for the Mem stage
• Register Files Write port (bus W) for the Wr
  stage
• One instruction enters the pipeline every cycle
• One instruction comes out of the pipeline
  (complete) every cycle
• The Effective Cycles per Instruction (CPI) is 1

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Conventional Pipelined Execution Representation
Time
Program Flow
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Single Cycle, Multiple Cycle, vs. Pipeline
Cycle 1
Cycle 2
Clk
Single Cycle Implementation
Load
Store
Waste
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Cycle 10
Clk
Multiple Cycle Implementation
Load
Store
R-type
Pipeline Implementation
Load
Store
R-type
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Why Pipeline? Because the resources are there!
Time (clock cycles)
I n s t r. O r d e r
Inst 0
Inst 1
Inst 2
Inst 3
Inst 4
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Can pipelining get us into trouble?

• Yes Pipeline Hazards
• structural hazards attempt to use the same
  resource two different ways at the same time
• E.g., combined washer/dryer would be a structural
  hazard or folder busy doing something else
  (watching TV)
• data hazards attempt to use item before it is
  ready
• E.g., one sock of pair in dryer and one in
  washer cant fold until get sock from washer
  through dryer
• instruction depends on result of prior
  instruction still in the pipeline
• control hazards attempt to make a decision
  before condition is evaulated
• E.g., washing football uniforms and need to get
  proper detergent level need to see after dryer
  before next load in
• branch instructions
• Can always resolve hazards by waiting
• pipeline control must detect the hazard
• take action (or delay action) to resolve hazards

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Single Memory is a Structural Hazard
Time (clock cycles)
I n s t r. O r d e r
Reg
Mem
Reg
Load
Instr 1
Instr 2
Mem
Reg
Mem
Reg
Instr 3
Instr 4
Detection is easy in this case! (right half
highlight means read, left half write)
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Structural Hazards limit performance

• Example if 1.3 memory accesses per instruction
  and only one memory access per cycle then
• average CPI