Doing the VCS Assignment

1
Doing the VCS Assignment

1. Download the Calc1 code
2. Unzip/Uncompress it
3. Go into the directory with the verilog code

There are several verilog files
including calc1_top.v - the main design
file testbench.v - contains the stimulus,
instantiates the design You will simulate
testbench.v This will force the
compilation/simulation of all other blocks
2
Running VCS

• Type vcs -RI testbench.v

• The Interactive Window appears

3
Waveform Window

• Open the Waveform Window
• Need to select the signals you want to see, use
  Hierarchy Window

4
Hierarchy Window

• Select the bigtest module to see its signals
• Drag-and-drop the signals into the Waveform Window

5
Waveform Window with Signals

• The signals are on display, but they are blank

6
Execute Simulation

• Simulate by selecting Continue
• Printed results are shown in top pane

7
Waveforms Results

• Waveform Window is updated with results
• Zoom out and scroll over time

8
Waveforms Results, Zoomed and Scrolled