CSE 140 Lecture 8 Sequential Networks

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CSE 140 Lecture 8Sequential Networks

• Professor CK Cheng
• CSE Dept.
• UC San Diego

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Part II. Sequential Networks (Ch. 3)
Memory / Time steps
si
xi
yi
yifi(St,X) sit1gi(St,X)
Clock
Memory Flip flops Specification Finite State
Machines Implementation Excitation Tables
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Memory Devices

• Memory Storage
• Latches
• Flip-Flops
• SR, D, T, JK
• State Tables
• Characteristic Expressions

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Memory Storage Capacitive Loads

• Fundamental building block of other state
  elements
• Two outputs Q, Q
• No inputs

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Capacitive Loads

• Consider the two possible cases
• Q 0 then Q 1 and Q 0 (consistent)
• Q 1 then Q 0 and Q 1 (consistent)
• Bistable circuit stores 1 bit of state in the
  state variable, Q (or Q )
• But there are no inputs to control the state

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SR (Set/Reset) Latch

• SR Latch
• Consider the four possible cases
• S 1, R 0
• S 0, R 1
• S 0, R 0
• S 1, R 1

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SR Latch Analysis

• S 1, R 0 then Q 1 and Q 0
• S 0, R 1 then Q 0 and Q 1

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SR Latch Analysis

• S 1, R 0 then Q 1 and Q 0
• S 0, R 1 then Q 0 and Q 1

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SR Latch Analysis

• S 0, R 0 then Q Qprev
• S 1, R 1 then Q 0 and Q 0

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y
S
y (SQ)
Q
Q (Ry)
R
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Flip-flop Components
SR F-F (Set-Reset)
y
S
R
Q
Inputs S, R State (Q, y)
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Id Q y S R Q y Q y
Q y 0 0 0 0 0 1
1 0 0 1 1 1 0 0 0
1 0 1 0 1 0 1 2
0 0 1 0 1 0 1
0 1 0 3 0 0 1 1
0 0 0 0 0 0 4 0 1
0 0 0 1 0 1 0
1 5 0 1 0 1 0 1 0
1 0 1 6 0 1 1 0
0 0 1 0 1 0 7 0
1 1 1 0 0 0 0 0
0 8 1 0 0 0 1 0
1 0 1 0 9 1 0 0 1
0 0 0 1 0 1 10
1 0 1 0 1 0 1 0
1 0 11 1 0 1 1 0 0
0 0 0 0 12 1 1 0
0 0 0 1 1 0 0 13
1 1 0 1 0 0 0 1
0 1 14 1 1 1 0 0
0 1 0 1 0 15 1 1 1
1 0 0 0 0 0 0
State
Q y
SR
Transition
State Diagram
00 01
10
00 10
10
01
10
01
11
10
01
11
10 SR
00
11
01
00
00 11
11
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CASES SR01, (Q,y) (0,1) SR10, (Q,y)
(1,0) SR11, (Q,y) (0,0) SR 00 gt if (Q,y)
(0,0) or (1,1), the output keeps
changing Solutions 1) SR (0,0), or 2) SR
(1,1).
State table
SR
inputs
00 01 10 11
PS
0 0 0 1 - 1 1 0 1 -
Characteristic Expression Q(t1) S(t)R(t)Q(t)
Q(t)
Q(t1)
NS (next state)
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SR Latch Analysis

• S 0, R 0 then Q Qprev and Q Qprev
  (memory!)
• S 1, R 1 then Q 0 and Q 0 (invalid
  state Q ? NOT Q)

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SR Latch Symbol

• SR stands for Set/Reset Latch
• Stores one bit of state (Q)
• Control what value is being stored with S, R
  inputs
• Set Make the output 1 (S 1, R 0, Q 1)
• Reset Make the output 0 (S 0, R 1, Q 0)
• Must do something to avoid
• invalid state (when S R 1)

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D Latch

• Two inputs CLK, D
• CLK controls when the output changes
• D (the data input) controls what the output
  changes to
• Function
• When CLK 1, D passes through to Q (the latch is
  transparent)
• When CLK 0, Q holds its previous value (the
  latch is opaque)
• Avoids invalid case when Q ? NOT Q

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D Latch Internal Circuit

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D Latch Internal Circuit

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D Flip-Flop

• Two inputs CLK, D
• Function
• The flip-flop samples D on the rising edge of
  CLK
• When CLK rises from 0 to 1, D passes through to Q
• Otherwise, Q holds its previous value
• Q changes only on the rising edge of CLK
• A flip-flop is called an edge-triggered device
  because it is activated on the clock edge

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D Flip-Flop Internal Circuit

• Two back-to-back latches (L1 and L2) controlled
  by complementary clocks
• When CLK 0
• L1 is transparent, L2 is opaque
• D passes through to N1
• When CLK 1
• L2 is transparent, L1 is opaque
• N1 passes through to Q
• Thus, on the edge of the clock (when CLK rises
  from 0 1)
• D passes through to Q

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D Flip-Flop vs. D Latch
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D Flip-Flop vs. D Latch
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Latch and Flip-flops (two latches)
Latch can be considered as a door
CLK 0, door is shut
CLK 1, door is unlocked
A flip-flop is a two door entrance
CLK 1
CLK 0
CLK 1
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D Flip-Flop (Delay)
Id D Q(t) Q(t1) 0 0 0
0 1 0 1 0
2 1 0 1 3 1 1
1
Q
D
CLK
Q
State table
Characteristic Expression Q(t1) D(t)
D
PS
0 1
0 0 1 1 0 1
NS Q(t1)
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JK F-F
State table
Q
J
JK
00 01 10 11
PS
CLK
0 0 0 1 ? 1 1 0 1 ?
Q
K
Q(t1)
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JK F-F
State table
Q
J
JK
00 01 10 11
PS
CLK
0 0 0 1 1 1 1 0 1 0
Q
K
Q(t1)
Characteristic Expression Q(t1)
Q(t)K(t)Q(t)J(t)
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T Flip-Flop (Toggle)
State table
Q
T
T
PS
0 1
CLK
0 0 1 1 1 0
Q
Q(t1)
Characteristic Expression Q(t1) Q(t)T(t)
Q(t)T(t)
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Using a JK F-F to implement a D and T F-F
Q Q
J K
D
CLK
D flip flop
Q Q
J K
T
CLK
T flip flop