The Continued Evolution of Re-Configurable FPGAs for Aerospace and Defense Strategic Applications

1
The Continued Evolution of Re-Configurable FPGAs
for Aerospace and Defense Strategic Applications

Howard Bogrow
2
Abstract
Present and future aerospace and defense
applications continue to demand ever
increasing performance, density, and above all
flexibility from FPGAs. The Virtex families of
re-configurable FPGAs provide the technology to
meet these demands. Various members of these
families are currently available in both COTs and
SMD formats, as well as in radiation tolerant
versions. Xilinx is also fully supporting a
recently announced software tool that automates
the implementation of TMR (Triple Modular
Redundancy) into members of these FPGA families
for mission critical applications. Xilinx has
received government funding towards the
development of a Single Event Immune
Re-configurable FPGA (SIRF) with possibly
strategic performance. This paper will focus on
Xilinx currently available Virtex solutions,
while also discussing Xilinx's future development
efforts. There will also be some discussion of
the various manufacturing flows utilized by
Xilinx to address the stringent requirements of
current and future space missions, as well as the
latest package developments.
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Xilinx Long-Term Commitment to Aerospace Defense
1st 90nm Virtex-4 Platform FPGA Rad tolerant
Virtex-II Pro
04
Xilinx on Mars
1st 130nm Virtex-II Pro SEE Consortium formed
02
1st 150nm Virtex-II Platform FPGA Rad tolerant
Virtex SPROMs
00
98
Virtex million-gate FPGAs 1st rad tolerant devices
1st 0.35 0.25mm FPGAs QML ISO9001
certifications
97
95
ISO 9002 certification
91
1st Standard Military Drawing (SMD) released
89
1st device qualified to MIL-STD-883
85
Introduced 1st field programmable gate array
(FPGA)
84
Xilinx Founded
1985 1990 1995 2000 2005
Source Company reports
4
Xilinx Technology Roadmap
180 nm

• Leading SIA Roadmap
• 150nm, 130nm and 90nm
• 300mm wafers starting with Virtex-II and Virtex-E
• First 90nm Spartan-3 family in full production
• First Virtex-4 devices now shipping

Virtex-E Extended Memory
150 nm
Virtex-II
SIA Roadmap
130 nm
Virtex-IIPRO
Virtex-4
90 nm
Spartan-3
65 nm
45 nm
1999
2000
2002
2003
2004
2005
2001
5
Aerospace and DefenseVirtex Mil Spec Products
65nm
Next Generation
Virtex-4
90nm
Mil-Temp Space Grades
Virtex-IIPRO
130nm
Mil-Temp Space Grades
Virtex-II
150nm
Mil-Temp Space Grades
180nm
Rad Tolerant
220nm
Rad by Design Program
2003 2004
2005 2006
6
Aerospace and Defense QualificationsClosing the
Gap with Commercial
Years from Commercial Production Qualification
4
XC3000
XQ4000XL
XC4000 XC4000E XQ4000EX
3
Virtex
Virtex-E
XQ4000XL
Virtex
Virtex-E
2
Military Qualification
1
Space Qualification
Program Goals
FPGA Family Generations
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Virtex-4 ASMBL ColumnarArchitecture

• Virtex 4th Generation advanced FPGA architecture
• Enables dial-In resource allocation mix
• Logic, DSP, BRAM, I/O, MGT,DCM, PowerPC
• Enabled by Flip-Chippackaging technology
• I/O columns distributed throughout the device

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Three Virtex-4 Platforms
LX
FX
SX
Resource
23-55K LCs
14-200K LCs
12-140K LCs
Logic Memory DCMs DSP Slices SelectIO RocketI
O PowerPC Ethernet MAC
2.3-5.7Mb
0.9-6Mb
0.6-10Mb
4-12
4-8
4-20
128-512
32-96
32-192
320-640
240-896
240-960
N/A
N/A
0-24 Channels
N/A
N/A
1 or 2 Cores
N/A
N/A
2 or 4 Cores
DSP
Density
Processor Cores
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Process Technology Advances

• Advanced 90-nm process
• 11-Layer metallization
• 10 copper 1 aluminum
• New Triple-Oxide Structures
• Lower quiescent power consumption
• Benefits
• Best cost
• Highest performance
• Lowest power
• Highest density
• Over 1 million 90 nm FPGAs shipped

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Dramatic Power Reduction in Virtex-4

• Challenges
• Static power grows with process generations
• Transistor leakage current
• Dynamic power grows with frequency
• P cv2f

Power Consumption
130 nm FPGAs

• Virtex-4 cuts power by 50
• Measured 40 lower static power with
  Triple-Oxide technology

50

• 50 lower dynamic power with 90-nm
• Lower core voltage
• Less capacitance

• Up to 10x lower dynamic power with hard IP
• Integration means fewer transistors per function

Frequency
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Virtex-4 Configuration Features

• Higher configuration speed
• 100MHz Serial Parallel interface
• 66MHz JTAG interface
• CCLK available to users
• 256 bit AES security
• Configuration ECC
• ICAP and DRP support
• Dedicated configuration I/O bank
• Enhanced partial reconfiguration
• Compatible with previous FPGAs
• Supports earlier configuration modes

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FPGA Radiation ToleranceTID Trends vs
Product/Technology

• 350nm - XQ4000XL
• 60 krad (Si)
• 220nm - XQVR (Virtex)
• 100 krad (Si)
• 150nm - XQR2V (Virtex-II)
• 200 krad (Si)
• 130nm XQR2VP
• 250 krad (Si)
• 90nm (Preliminary)
• 300 krad (Si)

• Process trends
• Gate oxide continues to thin
• Oxide tunnel currents increase
• Gate stress voltage decreases

See CMOS SCALING, DESIGN PRINCIPLES and
HARDENING-BY- DESIGN METHODOLOGIES by Ron
Lacoe, Aerospace Corp 2003 IEEE NSREC Short
Course 2003
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SEE Consortium Platform FPGA Test Phases

• Parallel Test Approach to accelerate product
  qualification
• 3 SEE Consortium Tiger Teams Fabric, Processor,
  Serial Transceiver

Dynamic (2Q05)
Mitigation (3Q05)
Special Solutions
Static (1Q05)
V-2pro
FPGA Fabric and Static Cells
V-2pro
PowerPC Processor IP
V-2pro
Multi-Gigabit Serial Transceivers
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Dose Rate Testing

• Current Test Program
• XC2VP40
• Work is funded by MDA
• Testing is being done by a consortium consisting
  of AFRL, Crane, Xilinx and Raytheon
• Initial tests were run July 2004 at Navsea Crane
  using 60 MeV electron beam source utilized
  commercial Virtex-IIpro performance board
  and commercial V-IIpro parts
• Tests to compare RH (epi) performed in November
  2004 at Navsea Crane
• No upset until gt 3.0E8
• RH (epi) no POR until gt1.0E9
• No Latch-up through gt1.0E10

• Historical Testing
• XC4036XL
• Testing was done by Lockheed
• Testing range of 1.0E7 to 4.0E11 (20 nsec pulse)
  tested
• No data upset gt1.3E9 to gt3.0E9
• No latch-up beyond 4.0E11
• XCVR300E
• Testing done by ITT (MRC)
• Testing range of 6.3E7 to 3.0E9
• No upset until gt 4.0E8 (non-epi) to gt1.0E9 (epi)
• No latch-up beyond 3.0E9

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TMRTool

• Software development tool to automatically
  implement TMR customer designs optimized for
  Xilinx FPGAs
• Result of Xilinx/Sandia National Labs partnership
• Released to Production in Sept 2004
• Support all design entry methods and HLLs
• NGO NGC based input
• EDIF based output
• OS Support
• Windows 2000/XP GUI Support
• Windows/UNIX PERL Command Line Support
• Supports ISE 5.2i, 6.1i, 6.2i

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TMRTool Netlist Flow
Xilinx Design Flow
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RadHard by Design Program SEU Immune
Reconfigurable FPGA (SIRF)
Configuration Memory Control Logic Logic
Fabric DSP Fabric
Block Memory
Clocking Clock Mgmt
RocketIOMulti-Gigabit Transceiver
SelectIO
PowerPC
Virtex-4Silicon Floorplan
Phase-1 Design Feasibility, Test Chip
Phase-2 Chip Development
Phase-2A Advanced Features
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SIRF Radiation Goals
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Advanced Packaging

• CG717
• 35 x 35mm body, 1.27mm pitch, cavity-up
• Footprint compatible with the BG728
• Developed for the 2V3000
• Wire Bond, gold
• Au-Sn lid (hermetically sealed)
• CF1144
• 35 x 35mm body, 1.00mm pitch
• Footprint compatible with the FF1152
• Developed for the 2V6000
• Flipchip with high lead balls, MSL1

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Enhanced Flow In Development
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Summary

• Virtex-4 architecture and design methodology
  enables rapid development of Platform-specific
  FPGAs with embedded cores
• Advances in 90nm chip design resulted in
  optimized performance, lower power, and
  first-silicon success of Virtex-4
• SEE Consortium primary vehicle for radiation
  characterization testing (US and European)
• Rad Tolerant program will continue with
  concurrent phase-in of Rad Hard by Design program
• Advanced packaging and enhanced process flows
  integral part of overall development efforts