ECE 426 - VLSI System Design

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ECE 426 - VLSI System Design

• Lecture 9 - ASM Diagrams
• February 26, 2003

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• Reading Wolf 8.3
• MOSIS Chips are IN!
• Breaking News Intels Prescott Pentium 4
  discussed at Intel Developers Forum
• 90nm process technology
• Clock gt3GHz (up to 5GHz w/ anticipated process
  improv.)
• 1 Mbyte L2 Cache
• 800 MHz front-side bus
• Strained Silicon
• 13 new instructions

Source EE Times 2/24/03
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Where we are...

• Last Time
• Review - Basic Concepts in Register-Transfer
  Design
• Datapath / Control Paradigm
• Testbenches for Register-Transfer Designs
• Design Guidelines
• ASM Diagrams
• Today - Register Transfer Design
• ASM Diagrams
• Handshaking

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ASM Diagrams

• ASM Algorithmic State Machine
• A flowchart notation for state machines
• Motivation
• High-level description of clock-cycle level
  behavior
• Alternative to traditional state diagrams
• Easier to read for large diagrams
• Prevents inconsistent diagram specifications
• More concise than Verilog code

Christopher R. Clare, Designing Logic Using
State Machines, McGraw-Hill, 1973
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Flavors of ASM Diagrams

• Low-level
• Cycle-by-cycle timing
• Detailed specification of input / output values
• Equivalent to standard state diagram
• Register-Transfer Level (book uses this)
• Cycle-by-cycle timing
• Abstract operations (can map directly to low
  level)

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ASM Elements
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Describing an ASM State
Note all other outputs are 0!
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State Description w/ Complex Branches
State Diagram Equivalent (Fill In)
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ASM Diagram Pitfall

• Conditional output boxes specify values
• Conditional output boxes dont specify sequence

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ASM Example - Successive Approximation Circuit
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ASM Example - Successive Approximation Circuit
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ASM Example

• ASM Diagram for Successive Approximation Circuit

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Example MIPS Multicycle Design
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Example MIPS Multicycle Design
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Multicycle Control - ASM Diagram Part 1
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Multicycle Control -ASM Diagram Part 2
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Multicycle Control -ASM Diagram Part 3
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RTEX
BR
ALUSrcA 1 ALUSrcB 00 ALUOp 10
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond PCSource 01
RTWB
RegDst 1 RegWrite MemtoReg 0
0
0
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RT-Level ASM

• Key idea
• Use same notation as regular ASM
• Instead of outputs, write register transfers
• Advantages
• Plan complex designs before details are nailed
  down
• Estimate resource costs by counting operations in
  each state

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Multicycle Control - ASM Diagram Part 1
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Multicycle Control -ASM Diagram Part 2
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Multicycle Control -ASM Diagram Part 3
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About Lab 5 - Serial Receiver
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Lab 5 Design

• Design circuit as a datapath / controller system
• General Approach
• 1. Wait for the falling edge of the START bit.
• 2. Delay to the center of the START bit and
  sample the current data value. If the data value
  is not still asserted low, ignore the START bit
  and return to step 1.
• 3. Delay to the center of the next data bit.
  Sample the value of the data value and shift it
  into a shift register.
• 4. Repeat step 3 seven more times.
• 5. Delay to the center of the stop bit and
  sample. If the value is not correct, indicate a
  framing error condition.
• 6. Indicate that valid data is available in the
  shift register.
• 7. Go back to step 1.

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Coming Up

• Multiple Controller / Datapath Designs
• Synchronization Issues with Multiple Controllers

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Verification Plan

• Definition A Specification of the Verification
  Effort
• Prerequisite Specification document for design
• Defnining Success - Must Identify
• Features which must be exercisedunder which
  conditions
• Expected Response

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Levels of Verification

• Board
• System / Subsystem
• ASIC / FPGA
• Unit / Subunit

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Levels of Verification

• Connectivity
• Transaction / Cooperative Data Flow
• Functionality
• Ad Hoc
• Designer verifies basic functionality

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Levels of Verification - Notes

• Stable interfaces required at each level of
  granularity

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System Design Issues

• ASM Diagrams
• Synchronization Metastability
• Handshaking
• Working with Multiple Clocks

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