Semiconductor Memories

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CHAPTER 6
Semiconductor Memories
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INTRODUCTION
Memory circuits provide the means of storing
information (data) on a temporary or permanent
basis and for future recalls. Magnetic
memory Generally is capable of storing large
amount of data at very low cost, but the access
time (the time it takes to locate and then read
or write) is usually very long. Semiconductor
memories use electrical signals to identify
memory location and its content. The access time
in several orders of magnitude faster that
magnetic memory. MOS and bipolar technologies
can be used to implement various types of
semiconductor memories.
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CLASSIFICATION OF SEMICONDUCTOR MEMORIES
Semiconductor memories
volatile
Non-volatile
SRAM, DRAM
ROM, EPROM
loose their data once the power supply is turned
off.
can retain their data even after power is
removed.
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STATIC RAM (SRAM)

• Random Access Memory (RAM) is a readable and
• write-able volatile memory.
• The term random access means that the user can
  access any location of the entire memory and in
  any order.
• RAM is further divided into static RAM (SRAM) and
  dynamic RAM (DRAM).
• Static RAM is a simple latch circuit (flip-flop)
  that remembers its state until it is toggled.

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STATIC RAM (SRAM)
The simplest SRAM would be a simple data latch
with pass transistors for selection and
isolation. The actual implementation is usually
carried out by the 6-transistor cell.
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STATIC RAM (SRAM)
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STATIC RAM (SRAM)
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DYNAMIC RAM (DRAM)
Fabricated using MOS technology and are noted for
their high capacity, low power requirement, and
moderate operating speed (when compared to
SRAM). DRAMs make use of MOS capacitors to store
the data as electronic charges. The capacitors
can be switched in and out of the bit lines via a
pass transistor. The storage capacitor will
loose its charge over time. Therefore, DRAMs must
be refreshed in a regular basis.
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DYNAMIC RAM (DRAM)
The read operation for DRAM is a destructive
process. Therefore, extra peripheral circuits
must be used to rewrite the DRAM cells as soon as
it is read. These operations are incorporated as
part of the DRAM chip and are transparent to the
users. The memory organization can be similar to
the SRAM array. However, the memory size for
DRAMs is usually much larger. Currently DRAM in
1G-bit size are available while SRAM sizes of
under a 1M-bit are more common.
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DYNAMIC RAM (DRAM)
The most important difference of the DRAM
fabrication process from other technology is the
storage capacitor. The single-transistor DRAM
cell requires a capacitor that can store
sufficient charge to allow the cell state to
state true between refresh cycles. The most
significant development in the DRAM devices has
been the advance in the capacitor design.
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DYNAMIC RAM (DRAM)
The DRAM capacitors have been improved in two
ways increasing the surface area and increasing
the capacitor dielectric constant
For a minimum Tox, the remaining adjustable
parameters are ei and A.
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Trenched DRAM Cell

• One area of progress in making a capacitor with a
  larger surface area is to form the capacitor in a
  trench.
• This technique make use of a deep trench (gt 7µm
  into the silicon).
• It has the advantage of allowing the
• transistors to be formed nearly planar
• on the surface with the trench extending
• below the device active area.

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Trenched DRAM Cell
The effect of the large surface area and the
ability to thin the gate dielectric by improving
the reliability of the thin oxides has resulted
in a DRAM that can store more charge in smaller
top surface area.
Fabrication results of Trenched DRAM Cell
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Stacked DRAM Cell
Another area of tremendous progress in DRAM
technology goes in the other direction and forms
the capacitors in geometries that extend above
the silicon to create a large capacitor
area. The large surface areas can be created
using a large planar capacitor shaped like a dome
or a crown. These structures also take advantage
of higher-dielectric constant materials for the
inter-level dielectric for the capacitors
Ta2O5 (Ba, Sr)TiO3, etc.
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Stacked DRAM Cell
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Trench Cell vs. Stacked Cell
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Trench Cell vs. Stacked Cell
In the trench technology, the cell process is
completed before the gate oxidation. Therefore
there is no thermal process due to cell capacitor
formation after the MOSFET formation. Another
advantage in the trench cell is that there is no
height difference between cell array region and
peripheral circuit region. In the stacked cell,
the height difference require high aspect ratio
contact holes and difficulty in the planarization
process after the cell formation. The MOSFET
formation steps are followed by the stacked
capacitor formation steps.
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Trench Cell vs. Stacked Cell
These include high temperature processing steps
such as storage node insulator (SiO2/SiN)
formation, SiN deposition for the self-aligned
contact formation, etc. Salicide (Self Aligned
siLICIDE) process for the source and drain of the
MOSFETs should be carefully designed to endure
the high temperature process steps. For
applications requiring Embedded DRAM, trenched
cell is more attractive because the DRAM cells
are formed before the MOSFETs and because there
is little height difference between the cell
array and other regions on the chip.
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READ ONLY MEMORY(ROM)
Certain applications may require the memory to
hold data that are either permanent or will not
be changed frequently.In this case, nonvolatile
memory is the candidate. As the name implies,
Read Only Memory (ROM) has no provision to write
or update its memory contents. The programming
is usually done during the manufacturing process
or by a burning procedure prior to field use.
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READ ONLY MEMORY
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READ ONLY MEMORY
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READ ONLY MEMORY
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READ ONLY MEMORY
One obvious disadvantage of the mask ROM is the
fact that a new photomask must be prepared if the
stored data is to be changed. This will also be
accompanied by a sizable turn-around time when
manufacturing the new ROMs. An alternate method
of implementing the ROM is with a programmable
technology such as fuse or anti-fuse. In this
case, the ROM becomes a programmable parts, hence
the name PROM. One advantage of the PROM is the
fact that all ROMs, regardless of data content
can be manufactured using the same set of
photomask and fabrication procedures.
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READ ONLY MEMORY
However, a one-time-only programming procedure
must be applied prior to field use. After the
PROM is programmed, its contents cannot be
changed anymore.
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READ ONLY MEMORY
Why EEPROMs?

• Field programmable capability to wireless
  portable telecommunication equipment
• ?? True 5V or lower operation
• ?? Compatible with CMOS/BiCMOS processes
• ?? High operation speeds and high density
• ?? Key to embedded systems
• ?? Solid-state nonvolatile memories
• ?? Multi-level Encoding

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Conventional Flash E2PROM cell Structures

• Similar to an ordinary MOSFET except for an extra
  gate buried in the silicon dioxide.
• Charges are stored in the floating gate to alter
  the threshold voltage of the E2PROM cell.
• Simple construction and fabrication steps
• Very high packing density
• Flash E2PROM and E2PROMs
• share the same technology

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Flash E2PROM Cell Operations

• For programming, hot electrons are created by the
• large drain bias current.
• These electron tunnels through the thin gate
  oxide and become trapped in the floating gate.

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Limitations of Existing Flash E2PROM Cells
Most cells suffer from hole trapping in the thin
gate oxide during erasing. Reduction in VTH
window after several cycles of erase and
programming.
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Memory Circuits
Semiconductor memories are comprised of a main
storage array surrounded by peripheral circuits
for read and write operations. These peripheral
circuits includes row and column address
decoders, data buffers/registers, sense
amplifiers, and charge pumps circuits. The
decoders and buffer/registers are basically
digital circuits and can be implemented using
conventional VLSI design methodology. The sense
amplifier is basically a high gain circuit that
is used to differentiate the stored information
with a reference voltage.
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Memory Circuits
This is especially critical if the storage
element is aDRAM cell. Most memory arrays
require separate high and low voltage supply to
operate. In order to eliminate the need for
multiple external power supplies, more memory
chips have built-in charge pump circuits to
generate multiple voltage levels from a single
supply (usually 5V or 3.3V).