Digital Testing: Sequential Circuits

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Digital Testing Sequential Circuits
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Outline

• Issues in testing sequential circuits
• Types of Tests
• Functional
• Deterministic
• Checking experiment
• Iterative array

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Importance of Sequential Circuits

• Most circuits are sequential
• The outputs depends on the input and
  the internal states
• Must drive the circuit first in a know state
  prior to applying the patterns that sensitize the
  faults to the outputs
• Use global reset or
• a synchronizing sequence
• Timing is an important factor
• Static and essential hazard

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Types of Tests

• Exhaustive 2is McCluskey 1981
• Pseudorandom Wunderlich 1989
• Not effective because it is not sufficient to
  apply the patterns, they should be done in the
  appropriate sequence
• Checking experiment
• Fault oriented, adaptation of combinational
  test
• Check literature for more recent algorithms

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Checking Experiment

• Synchronizing sequence SS place the FSM in a
  known state
• Homing sequence HS places the FSM in a known
  state that is identifiable by the output
  sequence
• Distinguishing sequence DS produces an
  output sequence that defines uniquely the
  initial state at which the sequence was applied
• Transition sequence TS indicates the
  transition form one state to any other

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State Table Verification for Sequential Circuit
Moore Theorem For any reduced strongly connected
(no equivalent states any state reachable from
another state) n-state sequential machine M,
there is an input-output sequence pair that can
be generated by M but can not be generated by any
other sequential machine with n or fewer
states This sequence is called checking sequence
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State Table Verification for Sequential Circuit
Given the state table of a sequential
machine, find an input /output sequence pair
(X,Z) such that the response to X will be Z iff
machine is fault free. Then (X,Z) is called
checking sequence and test is called checking
experiment
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State Table Verification for Sequential Circuit
Homing sequence is x101 since the final state
can be uniquely defined initial
state/output final state state A D,0 C,
0 C,1 B B,1 D,0 A,0 C C,1 B,0 B,1 D A,0 C,1 C,1

Example State table present
input state x0 x1 A C,1 D,0 B
D,0 B,1 C B,0 C,1 D C,0 A,0
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State Table Verification for Sequential Circuit
Definition Distinguishing sequence is such an
input sequence X that will produce different
output sequence for each initial state (so the
initial state can be distinguished) Every
distinguishing sequence is a homing sequence but
not opposite
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State Table Verification for Sequential Circuit

• Uncertainty is a collection of sates which is
  known to contain the present state.
• A successor tree is a structure which displays
  successor uncertainties for all input sequences
  xi
• A collection of uncertainties is an uncertainty
  vector
• An uncertainty vector whose components contain a
  single state, each is trivial
• A vector whose components contain single states
  or identical repeated states is homogeneous

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State table verification for sequential circuit
Algorithm to generate homing sequence Homing
sequence - path from root to trivial or
homogenous vector. Homing tree is a successor
tree in which a node becomes terminal if 1.
Non-homogenous components in an uncertainty
vector are the same as on the previous level 2.
Uncertainty vector is trivial or homogeneous
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State Table Verification for Sequential Circuit
Example Consider FSM
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Homing Sequence
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Algorithm to generate a distinguishing sequence
Distinguishing sequence - path from root to
trivial vector. A distinguishing tree is a
successor tree in which a node becomes terminal
if 1. Non-homogenous components in an
uncertainty vector are the same as on the
previous level 2. Uncertainty vector contains a
homogeneous non-trivial component (does not
have to be a homogeneous vector) 3.
Uncertainty vector is trivial
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State table verification for sequential circuit
Example Consider the following state table
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A successor tree
Finding distinguishing sequence
(ABCD) (ABD)(A) (BC)(CD) (A)(ABD)
(B)(CD)(C) (B)(A)(A)(D)
(D)(C)(BC) (B)(A)(D)(A) (D)(CB)(C)
(D)(A)(B)(A) (B)(C)(D)(C) (D)(A)(B)(A)
(B)(C)(D)(C)
1
0
0
0
1
1
0
0
1
1
1
0
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State table verification for sequential circuit
Example Consider FSM
Homogeneous component
No distinguishing sequence
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Distinguishing Sequence
Example Consider FSM, different output vectors
for different initial state
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Transfer Sequence
Transfer sequence - takes machine from one state
to another Example Consider previous FSM (no
transfer sequence)
Not strongly connected FSM
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Transfer Tree
Example Consider the following FSM
we get the transfer tree
To get from B to C we can select x 1,0
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State table verification for sequential circuit
Synchronizing sequence takes machine to the
specific final state regardless of the output or
initial state - does not always exists Example
Algorithm to generate synchronizing sequence
Consider the previous machine with
synchronizing sequence x 1,1,0
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Synchronizing Sequence
Example
1
0
0
1
0
1
0
0
0
1
1
1
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Designing checking experiments
Machine must be strongly connected diagnosable
( i.e. have a distinguishing sequence) 1.
Initialization (take it to a fixed states) a)
Apply homing sequence identify the
current state b) Transfer current state to S 2.
Identification (make machine to visit each state
and display response) 3. Transition
verification (make every state transition result
checked by distinguishing sequence)
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Designing checking experiments
Example Consider FSM
1. Initialization Successor tree
Found distinguishing sequence x 0,1 (so it is a
homing sequence as well) and the current state is
determined
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Designing checking experiments
Example (Initialization cont.)
After applying distinguishing sequence 0 1
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Designing checking experiments
2. Identification Visit each state and analyze
the results
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Designing checking experiments
3. Transition verification Check transition
from A to B with input 0, then apply
distinguishing sequence 01 to identify the
initial state before transition
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Designing checking experiments
Example Check transition from C to B with
input 0 and from C to A with input 1, and so on.
The entire checking test
time 1 2 3 4 5 6 7 8 9 10
11 input 0 0 1 0 0 1 1 0 1 0
0 state A B C B C A
D C output 1 0 0 0 0 0 0 1 1
1 0
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Designing checking experiments
time 12 13 14 15 16 17 18 19 20
21 input 1 1 0 1 0 1 0 0
0 1 state D A D
B A output 1 1 1 1 1 0
1 0 1 1
time 22 23 24 25 26 27 28 29 30
31 input 1 1 0 1 0 1 0 1
0 1 state D A C D
B D A output 1 0 0 1
1 0 1 1 1 0
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DFT for sequential circuits
Critical testability problems
1. Noninitializable design - change design to
have a synchronizing sequence 2. Effects of
component delays - check for hazard races in
simulation 3. Nondetected logic redundant
faults -do not use logic redundancy 4.
Existence of illegal states - avoid add
transition to normal states 5. Oscillating
circuit - add extra logic to control
oscillations
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DFT for sequential circuits
Checking experiments can not be applied for FSM
without a distinguishing sequence Modification
procedure for such FSM I. Construct testing
table upper part contains states
input/output pairs lower part contains
products of present next states with the
rule that (state)(-) (-) II. Construct testing
graph
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DFT for sequential circuits
Testing table for machine
Example state table
present input state x0 x1 A A,0 B,0
B A,0 C,0 C A,1 D,0 D A,1 A,0
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DFT for sequential circuits
II . Construct testing graph An edge Xp/Zp exists
directed from present state SiSj to next states
SkSl if SkSl (k ? l) is present in row SiSj
under Xp/Zp
Example for our machine we have
1/0 1/0
AB
AC
BC
1/0 1/0
1/0 1/0
BD
AD
CD
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DFT for sequential circuits
A machine is definitely diagnosable if its
testing graph has no loops and there are no
repeated states (i.e. no circled states in
testing table) so the example machine is not
definitely diagnosable In order to make machine
definitely diagnosable additional outputs (up to
k log ( states ) ) are required
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DFT for sequential circuits
Example (with added output)
After machine is modified to have distinguishing
sequence apply checking experiment procedure to
test it.
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Sequential Circuit Testing

• 1. Cut the few of the feedback wires to make the
  circuit acyclic
• 2. Each feedback wire is a pseudo input and a
  pseudo output
• 3. Consider different time frames decided by the
  clock and the inputs values
• 4. Use D-algorithm or any other to detect the
  faults
• 5. Start with the final time frame at which the
  fault is observed and trace backward to an
  earlier frame until the signal is justified
• 6. The PI cannot be assigned any values x? I ?
• 7. Repeat 5 until all signal are justified, if
  there is a conflict, trackback and select another
  justification path

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Sequential Circuit Model
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An Example
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Time Frames
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Another Example
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Time Frames Example 2
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EXAMPLE 1 TEST for p STUCK- AT - 0
Provoke Fault on p1 a10,
b11, Propagate Fault to S2 C01, a20,
b20 Justify C01 a01,
b01, Cinx
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Second input to e First input to h
Dont care
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1
0
1
1
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Delay Fault Tests

• At-Speed Test
• Operate circuits at rated speed
• Inputs functional, random, design verification
• Problems for tester at wafer probe
• Two Pattern Test (A Pair of Input Vectors)
• Robust delay test
• Hazard free test

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Test Generations Systems

• Classification
• Target a fault
• Reverse-time processing
• Forward-time processing
• Forward and reverse-time processing
• Target no specific fault
• Simulation based algorithms

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Test Generations Systems

• Reverse-time processing
• Determine a PO where the fault-effect will appear
• Backtrace within the time frame to excite and or
  propagate a fault/fault-effect
• If not possible go add a timeframe (previous
  timeframe) and continue

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Test Generations Systems Reverse-time processing

• Positives and Negatives

Low memory usages Timeframe added when
needed Ability to determine if a fault is
untestable
Hard to determine the PO where fault will be
detected During backward motion, often the
timeframe is assumed to be fault-free, this can
generate invalid tests Test application is in the
order opposite to test generation
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Test Generations Systems

• Forward-time processing
• Excite a fault in the present timeframe
• If excited, propagate to an output, else add a
  timeframe and then excite continue till fault
  excited
• Try to propagate the fault, if not successful,
  add timeframe and continue the process till fault
  detected at a PO

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Test generations systems Forward-time processing

• FASTEST approach
• Use controllability values to determine the
  timeframe where the fault can be excited
• Use observability values to determine the
  timeframe where the fault will be observed
• Together these will determine the number of
  timeframes need to detect the fault of interest
• Work with that many timeframes in combinational
  mode to generate a test sequence in forward time
• See example circuit (in class example)

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Test generations systems

• Forward and reverse-time processing
• Perform the fault effect propagation in forward
  time
• Perform excitation (justification) in reverse
  time using fault-free circuit

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Test Generations Systems Forward and
reverse-time processing

• Positives and Negatives

During backward motion, often the timeframe is
assumed to be fault-free, this can generate
invalid tests Test application is in the order
opposite to test generation
Medium memory usages Timeframe added when needed
in reverse as well as in forward time Ability to
determine if a fault is untestable
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Test Generations Systems

• General comments
• Store state information during test generation
  for later use
• Preprocess the circuit and learn about
  implication etc.
• Reuse previous solutions
• Modify easy/hard and SCOAP to better suit needs
  of the sequential ATPGs
• Make a better selection of the target fault as
  in FASTEST
• Neither 5-v nor 9-v are complete algorithms for
  sequential ATPG
• Multiple timeframe observation a possible
  solution but has not found way in practice

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Simulation based systems

• Difficulties with time-frame method
• Long initialization sequence
• Impossible initialization with three-valued logic
  
• Circuit modeling limitations
• Timing problems tests can cause races/hazards
• High complexity
• Inadequacy for asynchronous circuits
• Advantages of simulation-based methods
• Advanced fault simulation technology
• Accurate simulation model exists for verification
• Variety of tests functional, heuristic, random
• Used since early 1960s

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Using Fault Simulator
Vector source Functional (test-bench), Heuristic
(walking 1, etc.), Weighted random, random
Generate new trial vectors
No
Trial vectors
Stopping criteria (fault coverage, CPU time
limit, etc.) satisfied?
Fault simulator
Fault list
Yes
Restore circuit state
Update fault list
Test vectors
New faults detected?
Yes
Stop
No
Append vectors
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Contest

• A Concurrent test generator for sequential
  circuit testing (Contest).
• Search for tests is guided by cost-functions.
• Three-phase test generation
• Initialization no faults targeted
  cost-function computed by true-value simulator.
• Concurrent phase all faults targeted cost
  function computed by a concurrent fault
  simulator.
• Single fault phase faults targeted one at a
  time cost function computed by true-value
  simulation and dynamic testability analysis.
• Ref. Agrawal, et al., IEEE-TCAD, 1989.

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Phase I Initialization

• Initialize test sequence with arbitrary, random,
  or given vector or sequence of vectors.
• Set all flip-flops in unknown (X) state.
• Cost function
• Cost Number of flip-flops in the unknown state
• Cost computed from true-value simulation of trial
  vectors
• Trial vectors A heuristically generated vector
  set from the previous vector(s) in the test
  sequence e.g., all vectors at unit Hamming
  distance from the last vector may form a trial
  vector set.
• Vector selection Add the minimum cost trial
  vector to the test sequence. Repeat trial vector
  generation and vector selection until cost
  becomes zero or drops below some given value.

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Phase II Concurrent Fault Detection

• Initially test sequence contains vectors from
  Phase I.
• Simulate all faults and drop detected faults.
• Compute a distance cost function for trial
  vectors
• Simulate all undetected faults for the trial
  vector.
• For each fault, find the shortest fault distance
  (in number of gates) between its fault effect and
  a PO.
• Cost function is the sum of fault distances for
  all undetected faults.
• Trial vectors Generate trial vectors using the
  unit Hamming distance or any other heuristic.
• Vector selection
• Add the trial vector with the minimum distance
  cost function to test sequence.
• Remove faults with zero fault distance from the
  fault list.
• Repeat trial vector generation and vector
  selection until fault list is reduced to given
  size.

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Distance Cost Function
s-a-0
0
1
0
1
0
Trial vectors
Trial vectors
Trial vectors
Initial vector
0 1 1 1 0 1 0 0 1
0 0 0
1 0 0 0 1 0 0 0 1
0 1 1 0 1 0 0 0 1
2
2
2
0
1
8
8
8
8
8
Fault detected
Distance cost function for s-a-0 fault
Minimum cost vector
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Phase III Single Fault Target

• Cost (fault, input vector) K x AC PC
• Activation cost (AC) is the dynamic
  controllability of the faulty line.
• Propagation cost (PC) is the minimum (over all
  paths to POs) dynamic observability of the faulty
  line.
• K is a large weighting factor, e.g., K 100.
• Dynamic testability measures (controllability and
  observability) are specific to the present signal
  values in the circuit.
• Cost of a vector is computed for a fault from
  true-value simulation result.
• Cost 0 means fault is detected.
• Trial vector generation and vector selection are
  similar to other phases.

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Contest Result s5378

• 35 PIs, 49 POs, 179 FFs, 4,603 faults.
• Synchronous, single clock.

Contest 75.5 0 1,722 57,532 3 min. 9
min.
Random vectors 67.6 0 57,532 -- 0 9 min.
Gentest 72.6 122 490 -- 4.5 hrs. 10 sec.
Fault coverage Untestable faults Test
vectors Trial vectors used Test gen. CPU
time Fault sim. CPU time
Results provided by the developers of Contest
Sun Ultra II, 200MHz CPU
Estimated time Time-frame
expansion (higher coverage possible with more CPU
time)
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Genetic Algorithms (GAs)

• Theory of evolution by natural selection (Darwin,
  1809-82.)
• C. R. Darwin, On the Origin of Species by Means
  of Natural Selection, London John Murray, 1859.
• J. H. Holland, Adaptation in Natural and
  Artificial Systems, Ann Arbor University of
  Michigan Press, 1975.
• D. E. Goldberg, Genetic Algorithms in Search,
  Optimization, and Machine Learning, Reading,
  Massachusetts Addison-Wesley, 1989.
• P. Mazumder and E. M. Rudnick, Genetic Algorithms
  for VLSI Design, Layout and Test Automation,
  Upper Saddle River, New Jersey, Prentice Hall
  PTR, 1999.
• Basic Idea Population improves with each
  generation.
• Population
• Fitness criteria
• Regeneration rules

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GAs for Test Generation

• Population A set of input vectors or vector
  sequences.
• Fitness function Quantitative measures of
  population succeeding in tasks like
  initialization and fault detection (reciprocal to
  cost functions.)
• Regeneration rules (heuristics) Members with
  higher fitness function values are selected to
  produce new members via transformations like
  mutation and crossover.

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Strategate Results
s1423
s5378 s35932 Total
faults 1,515
4,603 39,094 Detected faults
1,414 3,639
35,100 Fault coverage 93.3
79.1 89.8 Test
vectors 3,943
11,571 257 CPU time
1.3 hrs. 37.8 hrs.
10.2 hrs. HP J200 256MB
Ref. M. S. Hsiao, E. M. Rudnick and J. H. Patel,
Dynamic State Traversal for Sequential
Circuit Test Generation, ACM Trans. on
Design Automation of Electronic Systems (TODAES),
vol. 5, no. 3, July 2000.
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Summary

• Combinational ATPG algorithms are extended
• Time-frame expansion unrolls time as
  combinational array
• Nine-valued logic system
• Justification via backward time
• Cycle-free circuits
• Require at most dseq time-frames
• Always initializable
• Cyclic circuits
• May need 9Nff time-frames
• Circuit must be initializable
• Partial scan can make circuit cycle-free (Chapter
  14)

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Summary (contd.)

• Sequential test generators classified
• FASTEST discussed
• Fault simulation is an effective tool for
  sequential circuit ATPG.
• Simulation-based methods produce more vectors,
  which can potentially be reduced by compaction.
• A simulation-based method and purely foreward
  time test generators cannot identify untestable
  faults.

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