Low Voltage Low Power constant - gm Rail to Rail CMOS Op-Amp with Overlapped Transition Regions

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Low Voltage Low Power constant - gm Rail to
Rail CMOS Op-Amp with Overlapped Transition
Regions

• ECEN 5007
• 9/3/02
• Vishwas Ganesan

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Motivation

• Low Supply Voltage Operation
• Constant gm
• Low power consumption making it suitable for
  portable applications.
• Reduced chip area.

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Why this paper came up ?

• Complementary differential pairs operate in
  parallel.
• This leads to one pair turned on and one off when
  input is near rails and both pairs on at the
  middle of the input range leading to gm being
  twice the value than the former case

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Other Circuit Proposals

1. Variation in the tail current in the differential
   paper doubling gm when only one pair is active.
2. Comparing currents from p and n differential
   pairs and the maximum current between them is
   selected and processed for gm constant by
   maximum-selecting circuitry.
3. Current bleed circuits
4. Square root circuit

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Difficulties with other circuits

• Increase in slew rate due to increase in tail
  current.
• Extra circuitry Signal processing circuits and
  many more current mirrors.
• All this leads to complication, Power consumption
  and more die.

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Complementary Input Stage

• Gm is constant if
• v (ßnIsn) v (ßpIsp) constant
• Cutoff Isn 0
• Vss Vcm Vn-
• Transition
• Isn Isn ( Vcm )
• Vn- lt Vcm Vn
• Saturation
• Isn ßMBn ( VGMBn Vss Vt n) 2
• Vn lt Vcm Vdd

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General Transition graph

• This shows the transition region overlap of a
  general n-p differential pair.

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Design
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Design
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Complementary Input Stage with DC Level Shifter

• Use a dc level shifter to shift the
• p-transition curve leftward to overlap the
  n-transition curve.
• Vshift small ? gm exceeds normal limit
• Vshift large ?gm drops below limit
• ? Voptimal yields constant Gm
• 2VGMBNlt?Voptimallt 2VGMBN v(Isno/ßM1)

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Plot Of gm vs Vcm
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OPAMP Circuit
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OPAMP Implementation

• DC level shifters implemented by 2 pairs of PMOS
  source followers MS1-MS4
• Three stages
• Complementary input stage
• Folded cascoded stage M21-M28 provides high gain
• Class AB output stage M30-M33
• MB1 and MB11 are biasing transistors.

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Frequency Response

• Amplitudes and phase plots show unstability due
  to varying gm.

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My simulation results
Input offset voltage 30 mV
Power dissipation .36 mW
Output Voltage swing 1.1 V to -1V
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Simulation plots
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Paper Results
Input offset voltage 3 mV
Power dissipation .31 mW
OpAmp area .12 mm2
Output Voltage swing Vss 0.04 to Vdd 0.07 V
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Conclusions

• DC level shifters can be used to overlap
  transition regions to obtain constant gm.
• Low Power dissipation was achieved
• Low supply voltages .
• There is considerable gain achieved leading to
  CMRR improvement.