Design Trends On Digital System Design

1
Design Trends On Digital System Design
2
Topics

• IC Technology
• Revolution
• Devices
• ASIP, ASIC, CPLD, FPGA
• Design Trends
• Co-design
• Embedded Computing

3
Semiconductor Technology Roadmap
4
The Revolution
First transistor Bell Labs, 1948
5
The First Integrated Circuits
Bipolar logic 1960s
ECL 3-input Gate Motorola 1966
6
Intel 4004 Micro-Processor
1971 1000 transistors 1 MHz operation
7
Intel Pentium (IV) microprocessor
2001 42 M transistors 1.5 GHz operation
8
Photo-Lithographic Process
optical
mask
oxidation
http//it.darden.virginia.edu/explore/content/inde
x_frames.htm
photoresist coating
photoresist
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from Fullman).
photoresist
development
acid etch
process
spin, rinse, dry
step
9
Moores law in Microprocessors
1000
2X growth in 1.96 years!
100
10
P6
Pentium proc
Transistors (MT)
486
1
386
286
0.1
8086
8085
0.01
8080
8008
4004
0.001
1970
1980
1990
2000
2010
Year
Transistors on Lead Microprocessors double every
2 years
Courtesy, Intel
10
Frequency
10000
Doubles every2 years
1000
P6
100
Pentium proc
Frequency (Mhz)
486
386
10
8085
286
8086
8080
1
8008
4004
0.1
1970
1980
1990
2000
2010
Year
Lead Microprocessors frequency doubles every 2
years
Courtesy, Intel
11
Power density
10000
1000
Power Density (W/cm2)
100
8086
10
4004
P6
8008
Pentium proc
8085
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low
temp
Courtesy, Intel
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Interconnect Delay
40
Gate delay
35
Interconnect delay
30
25
20
15
10
5
0
0.65 1989
0.5 1992
0.35 1995
0.25 1998
0.18 2001
0.13 2004
0.1 2007
Source SIA Roadmap 1997
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Trends in VLSI

• Transistor
• Smaller, faster, use less power
• Interconnect
• Less resistive, faster, longer (denser design)
• Yield
• Smaller die size, higher yield

14
Technology on Semiconductor
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TSMC
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Design Methodology
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Design Styles

• Full-Custom Design
• Standard Cell Design
• Gate Array Design
• Field Programmable Gate Array Design (FPGA)
• or mixtures of the above

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Full-Custom Design

• No rigid restrictions on layout.
• More compact design.
• Longer design time.
• Hierarchical chip ? clusters ? units ?
  functional units.

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Standard Cell Design

• Rectangular cells of the same height.
• Cell library (has 500 - 1200 cells).
• Cells placed in rows and space between rolls are
  called channels for routing.
• Feedthroughs

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Gate Array Design

• Each chip is prefabricated with an array of
  identical gates or cells.
• The chip is customized by fabricating routing
  layers on top.
• For example, MPGA

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Field Programmable Gate Array

• Chips are prefabricated with logic blocks and
  interconnects.
• Logic and interconnects can be programmed (erased
  and re-programmed) by users. No fabrication is
  needed.
• Interconnects are predefined wire segments of
  fixed lengths with switches in between.
• For example, FPGA, CPLD

22
Trends in Design Styles

• More complex system
• Digital and Analog IC (Mixed Signal)
• Hardware and Software Codesign
• SoC, SoPC
• Resulting in
• Higher abstract design level
• Advanced design tools to automate complex designs
• Short design time to compete market share

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Chip Devices
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Category

• General Propose
• CISC Complex Instruction Set Computer
• RISC Reduced Instruction Set Computer
• Specific Propose
• ASIP Application Specific Instruction Processor
• ASIC Application Specific IC
• Reconfigurable Hardware
• CPLD
• FPGA

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CISC vs RISC

• CISC
• Single memory for both data and instruction.
• Typical PC architecture
• Many instructions, some of them very complex
• Makes programming easier
• RISC
• Register rich. Data and instruction are kept in
  different memories.
• Fewer Instructions
• Fixed instruction length
• Fixed execution time

Pentium is a combination of both CISC and RISC!
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ASIP

• Excellent tradeoff between efficiency of ASIC and
  flexibility of DSP
• Specific code generator required
• Code generator must be generated automatically
  from description of processor
• From register description and instruction set
  (behavior)
• From structure of ASIP data path as generated by
  high level synthesis (structure)

27
ASIC

• A circuit custom-designed for a specific
  application is integrated onto a single silicon
  chip.
• Commercial chips are scarce and often require
  modification
• Specialized expertise to carry out a new, custom
  design
• Long development periods
• Can be costly and have schedule risk
• Low power, Small size, Fast

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ASIP vs ASIC
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Need Programmable Hardware?

• Benefits
• Non-permanent customization and application
  development after fabrication
• Economies of scale
• Time-to-market (evolving requirements and
  standards, new ideas)
• Low risk
• Drawbacks
• Efficiency penalty (area, performance, power)

30
MPGA

• MPGA (Mask Programmable Gate Array) is the first
  design way to make hardware programmable and gain
  more flexibility.
• Sea of Gates

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CPLD vs FPGA

• CPLD
• Rom-based
• Low density (Thousands gates)
• and-or plane (sum of product)
• Slow configuration time
• FPGA
• Ram-based
• High density (Thousands Multimillions gates)
• LUT (Look-up-table structure)
• Fast configuration time (ISP, runtime-reconfigurat
  ion)

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FPGA Basic Structure
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CLB Structure (Xilinx)

• Each slice has 2 LUT-FF pairs with associated
  carry logic
• Two 3-state buffers (BUFT) associated with each
  CLB, accessible by all CLB outputs

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LUT (Look-Up Table)

• Look-Up tables are primary elements for logic
  implementation
• Each LUT can implement any function of 4 inputs

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Routing Resources
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Basic I/O Block Structure
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More Guts in Modern FPGA

• RAM blocks (512 512Kbit)
• Dedicated multipliers (18x18 _at_200MHz)
• Transceivers (Multi-Gigabit I/O)
• Processor hard/soft cores (ARM, PowerPC, NIOS,
  MicroBlaze)
• DSP blocks (MAC, MULTADD)

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FPGA Usage
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Implementation Levels
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FPGA for ASIC Prototyping
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System Integration
Board Level Integration
MCM, SoP
SoC, SoPC
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Benefits

• Less components
• Component costs
• Board size and cost
• Assembly and testing costs
• Less inter-chip interconnects
• Reliability
• Power consumption
• Board design, fabrication and assembly costs
• Smaller system volume (in cm2) and weight
• Higher integration rate
• Smaller case costs
• Smaller transport costs
• In high volumes (in pcs), also lower circuit
  costs

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SoPC

• System-on-a-Programmable Chip (SOPC) term coined
  by Synopsys
• SoPC is a FPGA technology based user programmable
  solution
• PR and programming done by the user
• No delay on prototype production
• No delay on mass production start
• No NRE (production start) costs
• Production tests done by the IC vendor
• Design resource and time savings in the design
  flow
• Quick and cheap modifications

44
SoC vs SoPC

• SoC manufacturing is costly
• Foundries more and more expensive
• Mask costs for fine-grain lithography are
  increasing
• Silicon vendors concentrate on big customers with
  big quantities
• Very few multi-project prototype services
  available
• Malfunction will cost a lot of money and time
• Full-wafer prototype round may cost even 500,000
  ... 1M
• FPGA-type solutions are also evolving
• On-chip processor cores
• Multi-million gate capacity
• Some vendors also provide coarse-grain
  reconfigurability
• FPGA-based SoC-type platforms thus have a growing
  niche

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Hardware/Software Codesign Systems
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Why Co-design

• Hardware (ASIC, FPGA)
• Fast
• But very expensive
• Software (Processor)
• Flexible
• But slow
• Hardware Software Good solution?
• Requirements?

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HW/SW Cost Trend
100
Hardware
80
Development
60
Percent of total costs
40
Software
20
Maintenance
0
1955
1970
1985
2000
Year
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Software Acceleration
Task is sequential units of computations
contained in an application.
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Example of Digital Camera
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Traditional Design Flow
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HW/SW Codesign Flow

• Concurrent design between hardware and software
  using
• Co-simulation
• Co-synthesis

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Codesign in Reconfigurable System

• FPGA as hardware
• Reconfiguration can be applied an unlimited
  number of times.
• Compile-time configuration
• Run-time reconfiguration
• More flexible
• Hardware reuse

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Temporal and Spatial
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Interface IP Design

• IP based design is the process of composing a
  new system design by reusing existing components.

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More Complicated System
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Reconfigurable Processor
RAM
CPU
FPGA
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Embedded Computing
Source Rabaey, Sasimi04
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What is an embedded system?

• Systems which use computation to perform a
  specific function
• embedded within larger devices
• often completely unrecognized by the devices
  user
• Examples home appliances, office automation,
  consumer electronics, smart buildings, sensor
  nets, wearable electronics, automobiles

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Diversity in Embedded Computing

• Pocket remote control RF transmitter
• 100 KIPS, crush-proof, long battery life
• Software optimized for size
• Industrial equipment controller
• 1 MIPS, safety-critical, 1 MB memory
• Software control loops
• Military signal processing
• 1 GFLOP, 1 GB/sec IO
• Software for high performance.

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Trends in Embedded Systems

• Increasing code size
• average code size 16-64KB in 1992, 64K-512KB in
  1996
• migration from hand (assembly) coding to
  high-level languages
• Reuse of hardware and software components
• processors (micro-controllers, DSPs)
• software components (drivers)
• Increasing integration and system complexity
• integration of RF, DSP, network interfaces
• 32-bit processors, IO processors

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Embedded system metrics

• Some metrics
• performance MIPS, reads/sec etc.
• power Watts
• cost Dollars
• Software and architecture
• Instruction set, code density, register
  organization, caches, addressing, data types etc.
• MIPS, Watts and cost are related
• technology driven
• to get more MIPS for fewer Watts
• look at the sources of power consumption
• use power management and voltage scaling

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MIPS vs. Watts
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MIPS/W/
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Bandwidth vs. Watt and
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BW/W/ with hard disk
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Standby power
Here is why cell phone battery lasts longest, PDA
shorter and IPOD only a few hours
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New Design Themes

• Long-lived systems that can be untethered and
  unattended
• Low-duty cycle operation with bounded latency
• Exploit redundancy
• Data processing inside the network
• Exploit computation near data to reduce
  communication
• Self configuring/adaptive systems that can be
  deployed ad hoc
• Measure and adapt to unpredictable environment
• Exploit spatial diversity and density of
  sensor/actuator nodes

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Enter Wireless Design Challenges

• Wireless
• limited bandwidth, high latency (3ms-100ms)
• variable link quality and link asymmetry due to
  noise, interference, disconnections
• Mobility
• causes variability in system design parameters
  connectivity, b/w, security domains, location
  awareness
• Portability
• limited capacities (battery, CPU, I/O, storage,
  dimensions)

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Computing Technology Trend
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Smartphone vs Tablet
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SW (OS technology)
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SW (OS technology)
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HW technology

• http//www.youtube.com/watch?vttuzw9qso8s
• http//www.youtube.com/watch?vqripuN9Xdxsfeature
  related

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Thank You