Structure and Physical Operation

1
Chapter 4

• Structure and Physical Operation
• I -V characteristics
• MOSFET DC circuits
• CMOS Inverter
• MOSFET amplifiers
• Biasing MOSFETS
• High Frequency MOS model
• SPICE MOSFET model parameters

2
MOSFET ID-VG, ID-VDS
Output Charc.
Input Charc.
IDsat ?n Cox W/L (VGS - VTN)2/2 --- SQUARE LAW
Lgt?250nm
3
MOS Structure
4
MOS Transistor Operating Regions
VDD
VDD
5
MOS Transistor Operation-OFF
6
Triode or Linear Region
OFF VGS lt VT or VTO
7
Increasing VDS ID saturates
8
Cgs

• ON/Triode ?V gt 0 or VGS gt VTO
• Cgs WL Cox ?V gt VDS
• OFF ?V lt 0 or VGS lt VTO
• Cgs ? WL Cox
• Sat ?V lt 0 or VGS lt VTO
• Cgs 2/3 WL Cox ?V lt VDS

NMOS
N Diffusion
PMOS
P Diffusion
PolySilicon
9
Significant Process Parameter Constants
10
SPICE MODEL parameters
Over 200 parameters define Modern 65nm MOSFETs
2000nm
11
ID vs. VGS VDS gt ?V
L gt 250nm Square Law L lt 250nm Vel. Sat.
12
ID vs. VGS VDS gt ?V
Supplemental
Taking the square root of ID and solving for
slope intercept Extract VTO and KP
13
Enhancement/ Depletion Mode

• NMOS 1st Quadrant
• PMOS 3rd Quadrant
• Enhancement
• VTN gt 0V
• VTP lt 0V
• Depletion Mode
• VTN gt 0V
• VTP lt 0V

14
MOSFET parameters Ex -graphical
?V lt VDS
ID W/L ?n Cox (VGS - VTN)2/2 --- Sat. ?n Cox
W/L ? ID W/L ?n Cox ?V VDS
VDS2/2---Triode or Lin Region
15
CMOS Inverter Strong pull up down

• Rise time Fall Time

16
INVERTER POWER
Supplemental
17
The Digital CMOS inverter
Supplemental
18
CMOS Logic
19
CMOS Logic
NMOS pull dwn Zbar A?BC?D
20
CMOS Logic
PMOS pull UP Z AB ? CD
21
CMOS Logic
PMOS pull UP Z AB ? CD
22
CMOS Logic
PMOS pull UP Z AB ? CD
Supplemental
23
CMOS Logic
Supplemental
24
CMOS Logic Scaling
If CL? 3 minimum loads or 7.5fF 1/2 um process OR
0.25fF 90nm process tr tf equal?
25
CMOS Logic Scaling
gt 300X less Pwr
26
CMOS Logic
NMOS pull DWN Z A(DE) (B?C)
PMOS pull UP Z A(D ? E) ? (BC)
PMOS pull UP Z AB C
Supplemental
NMOS pull DWN Z A?B?C
27
CMOS Analog ID vs. VDS
28
CMOS Analog ID vs. VDS
Early Voltage and Lambda
Take Away effective output resistance Modeled
by 1/?ID or VA/ID
29
ID vs. VGS - ID vs. VDS
Amplification
30
Common Drain in ICs
31
ID vs. VGS - ID vs. VDS
Amplification
32
Q pt Bias Stabilization
Amplification
33
Q pt Bias Stabilization
Amplification
34
f1 Bias Considerations
Amplification
35
f2 Considerations
Amplification
36
Common Source
Summary
Select Qpt (VGS, ID, VDS) and estimate gm and
gds ID/VA Stabilize the Bias or Quiescent point
VGG VGSQ ID RS RG1, RG2 and RS VGG VDD
RG1/RG1 RG2 Determine Cc1, Cc2, CS
Determine RD after finding gm and gds. gain
-gm RDrdsRL mid band gain Generally RL gtgt
RD or rds RG RGRG gtgt Rgen
37
Common Source
Summary
38
Why CMOS Inverter
NMOS
PMOS
39
Complimentry CMOS Symbols
40
Large Signal Equivalent Ckt
41
Modeling rout
Supplemental
42
Supplemental
43
Misc. Effects
Supplemental
44
MOSFET DC BIAS
45
Shifting the Qpt for Gain A
Gain A ?VDS/ ?VGS
46
Distorting the Signal
Distortion
47
Shifting the Qpt cont
Analytical
?ID
?VGS
gm ?ID/ ?VGS
48
MOSFET DC BIAS
49
MOSFET DC BIAS-CS,CD,CG
Gain modest Rin High Ro High Inverting
Gain modest Rin low Ro High noninverting
Gain Unity Rin High Ro Low Noninverting
buffer
50
Bias Stabilization Depletion Enhancement
51
MOSFET Small Signal Equivalent Ckt
52
CS small signal equivalent Ckt
53
CS small signal eqivalent Ckt
54
CS small signal eqivalent Ckt
55
Modeling the Body effect
56
Biasing in Integrated MOS Amps
57
Current Steering
58
IC Biasing of the Basic MOS amps
59
Common Source amp in ICs
60
Common Gate in ICs
Supplemental
61
High Frequency MOSFET model
62
MOSFET fT
63
JFET I-V Characteristics
64
SPICE para Review