Techniques for and DSP Software Implementation of IEEE 802.16a TDD OFDMA Downlink Pilot-Symbol-Aided Channel Estimation - PowerPoint PPT Presentation

1 / 26
About This Presentation
Title:

Techniques for and DSP Software Implementation of IEEE 802.16a TDD OFDMA Downlink Pilot-Symbol-Aided Channel Estimation

Description:

Title: PowerPoint Presentation Last modified by: ChingChen Created Date: 1/1/1601 12:00:00 AM Document presentation format: Other titles – PowerPoint PPT presentation

Number of Views:145
Avg rating:3.0/5.0
Slides: 27
Provided by: ceeNctuE
Category:

less

Transcript and Presenter's Notes

Title: Techniques for and DSP Software Implementation of IEEE 802.16a TDD OFDMA Downlink Pilot-Symbol-Aided Channel Estimation


1
Techniques for and DSP Software Implementation of
IEEE 802.16a TDD OFDMA Downlink
Pilot-Symbol-Aided Channel Estimation
  • Student Chen, Ching
  • Advisor Prof. D. W. Lin
  • Time 2005/6/1

2
Outline
  • Review of frequency and time domain
    interpolation approaches
  • Frequency Linear and 2nd-order interpolation
  • Time 2-D interpolation
  • Simulation results
  • DSP code acceleration
  • Conclusion future work
  • Reference

3
LS Estimator
  • LS estimation objective
  • Channel matrix considering pilot carriers only
  • The Transform can reformulated
  • LS estimator

4
Interpolation in Frequency domain? Linear
Interpolation
  • The need for interpolation
  • Mathematical expression
  • Example

5
Interpolation in Frequency domain ? Second-Order
Interpolation
  • Mathematical expression
  • Example

6
Interpolation in Time domain ? 2-D Interpolation
  • We have
    pilots
  • to do interpolation.

7
Interpolation in Time domain 2-D Interpolation
  • Using previous symbol information with 2 kinds of
    formulas
  • (1) Formula 1
  • (2) Formular 2

8
Channel Model
  • ATTC (Advanced Television Technology Center) and
    the Grande Alliance DTV Laboratorys ensemble E
    model
  • 6-tap multi-path channel

9
Simulation on Static Channel
  • Comparison between 1st and 2nd formulas by using
    linear interpolation
  • MSE
    SER

10
Simulation on Static Channel
  • Comparison between 1st and 2nd formulas by using
    2nd-order interpolation
  • MSE
    SER

11
Simulation on Static Channel
  • Comparison between linear and 2nd-order
    interpolation by using 1st formula.
  • MSE

    SER

12
Simulation on Static Channel
  • Comparison between linear and 2nd-order
    interpolation by using 2nd formula.
  • MSE
    SER

13
Simulation on Rayleigh Fading Channel fdT0.01,
V27km/h
  • Comparison between linear and 2nd-order
    interpolation by using 2nd formula.
  • MSE

    SER

14
Simulation on Rayleigh Fading Channel fdT0.02,
V54km/h
  • Comparison between linear and 2nd-order
    interpolation by using 2nd formula.
  • MSE
    SER

15
Summation
  • 1st formula works better than 2nd one when
    suffering static channel condition.
  • Linear interpolation performs almost the same
    with 2nd-order one on static channel but better
    on rayleigh fading channel .
  • Besides, it is of low complexity.

16
DSP Acceleration
  • Data type modification.
  • Using intrinsic functions.
  • Coding style optimization.

17
Different Data Types Simulation
ResultsFloating-point v.s. Fixed-point 32 bits
Function Name Floating-point Code size (Bytes) Floating-point ExecutetionCycles Fixed-point 32bits Code size (Bytes) Fixed-point 32bits Executetion Cycles Improve-ment
Complex_Multiplier 284 899,603 484 88,513 90.16
Complex_Divier 404 1,900,051 440 688,850 63.75
Linear_Interpolation 548 579,794 632 441,423 23.87
64QAM 580 92,169 456 104,458 -13.33
De-64QAM 2472 1,305,239 1088 225,016 82.76
18
Different Data Types Simulation
ResultsFixed-point 32 bits v.s. Fixed-point 16
bits
Function Name Fixed-point 32bits Code size (Bytes) Fixed-point 32bits Executetion Cycles Fixed-point 16bits Code size (Bytes) Fixed-point 16bits Executetion Cycles Improve-ment
Complex_Multiplier 484 88,513 324 71,493 19.23
Complex_Divier 440 688,850 280 283,122 58.89
Linear_Interpolation 632 441,423 356 139,365 68.43
64QAM 456 104,458 440 104,458 0
De-64QAM 1088 225,016 1076 224,055 0.4
19
Different Coding Style Simulation Results
Function Name Fixed-point 16bits Code size (Bytes) Before Fixed-point 16bits Executetion Cycles Before Fixed-point 16bits Code size (Bytes) After Fixed-point 16bits Executetion Cycles After Improve-ment
Complex_Multiplier 324 71,493 488 7,686 89.25
Complex_Divier 280 283,122 348 201,427 28.86
Linear_Interpolation 356 139,365 308 132,442 4.97
64QAM 440 104,458 404 104,458 0
De-64QAM 1076 224,055 1052 218,894 2.3
20
Using Intrinsic Functions
  • For TI C6000 DSP
  • Special functions which have best optimized
    assembly code on the TI DSP architecture
  • (1)_amemd8_const Allows aligned loads of 8 bytes
    to memory.

21
Using Intrinsic Functions
  • (2)_dotp2 _dotpn2 Works for complex
    multiplier.
  • (3)_add2 32 bits adder .

22
Simulation Results by Using Intrinsic Functions
Function Name Fixed-point 16bits Code size (Bytes) Before Fixed-point 16bits Executetion Cycles Before Fixed-point 16bits Code size (Bytes) After Fixed-point 16bits Executetion Cycles After Improve-ment
Complex_Multiplier 488 7,686 268 3,426 55.42
Complex_Divier 348 201,427 428 193,764 3.8
Linear_Interpolation 308 132,442 308 132,442 0
64QAM 404 104,458 404 104,458 0
De-64QAM 1052 218,894 1052 218,894 0
23
Different Coding Style Simulation
Results(Interpolation, De-QAM)
Function Name Fixed-point 16bits Code size (Bytes) Before Fixed-point 16bits Executetion Cycles Before Fixed-point 16bits Code size (Bytes) After Fixed-point 16bits Executetion Cycles After Improve-ment
Complex_Multiplier 268 3426 272 3421 0
Complex_Divier 428 193,764 428 162,960 15.89
Linear_Interpolation 308 132,442 332 74,066 44.08
64QAM 404 104,458 396 101,308 3.02
De-64QAM 1052 218,894 1068 148,169 32.31
24
Performance Comparison between Floating-point and
Fixed-point version
  • MSE
    SER

25
Future Work
  • More optimization of DSP code.

26
Reference
  • Chen, Ying Ying , Study and Techniques of IEEE
    802.16a TDD OFDMA Downlink Channel Estimation,
    June 2004
  • Texas Instrument, TMS320C6000 Optimizing Compiler
    User Guild, literature no. SPRU187K, Oct. 2002.
  • Texas Instrument, TMS320C6000 Programmers guide,
    literature no. SPRU198F, Feb. 2001.
Write a Comment
User Comments (0)
About PowerShow.com