Design Slides for QM Port to techX

1
Design SlidesforQM Port to techX
Fred Kuhns Sailesh Kumar John DeHart
2
QM Architecture Changes
3
Dispatcher
4
Dispatcher

• Doesnt do any Queue ID adjustment
• Only forwards the packets to the appropriate QM
• Takes care of Plugin bit
• Requires to process Multi-copy packet
• Allocates common reference pointer and sets copy
  count
• Requires an interface to SRAM (via SRAM arbiter)
• Packets with drop bit set is sent to drop manager
• Should we remove this interface??
• Most of the code will be reused

5
Queue Length Controller
6
Queue Length Controller

• QLENC implements packet discards
• manages queue lengths of queues in block RAM
• Block RAM of every QLENC is externally accessible
• CCP can configure discard threshold and read
  queue length
• GCI takes in requests from CCP and sends to
  appropriate QLENC
• Note that QM doesnt require queue lengths
• Forwards the packets
• Admitted packets to QM
• Discarded packets to Drop manager
• Again, most of the QLENC code remains as it is

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Queue Manager
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Queue Manager

• One Constant Number of queues
• Has its own block RAM for queue header table
• Implemented as a circular list for WDRR
• Doesnt implement leaky bucket (only WDRR)
• Dequeue whenever allowed
• Constrained by the OUTC (OUTC sends ready to
  every QM)
• Doesnt identify any Flags
• Significant code changes, though most will be
  deletes

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Output Controller
10
Output Controller

• Keeps a small 2 deep (may be 1) FIFO for every QM
• Implements a leaky bucket for each QM
• Is it better than having leaky buckets at QM ???
• Obtains packet pointer for multi-copy packets
• Decrements copy count
• Frees up pointers for multi-copy packets, as copy
  count is zero
• Decent code changes (addition of leaky bucket and
  polling for ready QM data)

11
Drop Controller
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Drop Controller

• Forwards packets dropped by
• Dispatcher (Or QLENC in case Dispatcher interface
  is removed)
• Queue Length Controller due to threshold discard
• Multi-copy packet processing ???
• What should be done when a multi-copy packet is
  dropped
• Its possible that a multi-copy packet is dropped
  by one QM but admitted by another
• How to co-ordinate under this situation
• Solution
• Combine Drop manager and OUTC
• Process drop packets in the same manner, i.e.
  decrement copy count and free up pointers when
  copy count is zero
• Suggestions??

13
Global Control Interface
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Global Control Interface

• Provides external interface to QM memories
• Currently only Queue length/threshold memory
• Each memory location in QM will have a unique
  address
• MSB of address will choose appropriate QM
• Can be written or read via GCI
• CCP will talk thru GCI (Design GCI such that CCP
  interface remains the same)
• Least priority requester
• New block, but should be pretty straight forward

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Interfaces
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Critical Interface

• Process l and d should be faster than q and c for
  unicast packets
• So FIFOs can be just 1 deep (will be register
  with a ready)
• Requires leaky bucket rates to be stored in
  registers, which indeed is the case
• For multi-cast, l and d may be slower, so FIFOs
  may need to be 2/3 deep.

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Questions

• How will leaky bucket parameters be set?
• CCP, right.
• Free pointer controller
• Is it part of QM?
• Drop manager and OUTC should be a single piece of
  logic?

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• This architecture will clearly eat more logic
• But it is also more pipelined
• Also it be more manageable, flexible and simple
• Sounds like lot of work!!!
• Design and coding shouldnt take more than 2-3
  weeks
• Verification will take significant amount of time

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Current QM
CCP
Free Pointer Controller
16
36
SRAM Arbitrator
96
96
32
Queue Length Controller (QLNC)
36
Line Queue Manager (LNQM)
32
SRAM
36
CARL
48
DISPATCHER (DCHR)
Queue Header Controller (QHDC)
36
36
Switch Queue Manager (SWQM)
32
36
36
36
OSAR

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Output Controller (OUTC)
LC PSM
32
16
SW PSM
32
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QM Overview
There are two circular queues (for LC and SPC)
Packet Headers
Queue Headers
Current Queue
Previous Queue
Only the active queues are linked
Queue Header Table (on-chip Memory)
External SRAM
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Current CARL/QMGR Interface
95
64
73
80
88
77
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Flags (8 bit)
Queue Identifier (10 bit)
Internal Flags (8 bit)
Cpy Cnt
MB
DP
RC
NM
EX
HO
HR
FM
TO
DG
SB
SR
IC
FC
LP
SC
--
9
16
13
15
31
0
19
24
29
63
32
51
56
61
PPN
Packet Pointer (20 bit)
OVIN (5 bit)
31
0
10
16
24
Total Length (11 bit)
LFS Rate2
LFS Rate1
CARL to QMGR Interface
0
8
31
16
24
Flags (8 bit)
Internal Flags (8 bit)
LFS Rate2
LFS Rate1
DP
RC
NM
EX
HO
HR
FM
TO
DG
SB
SR
IC
FC
LP
SC
--
21
31
0
19
22
Queue Identifier (10 bit)
MB
Packet Pointer (20 bit)
0
10
29
31
24
PPN
OVIN (5 bit)
Total Length (11 bit)
0
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Queue Length (24 bit)
QMGR to OSAR Interface
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Current Flags
N
N-15
N-7
External Flags (8 bit)
Internal Flags (8 bit)
In code, IC is called FC (First copy) and is
used Thus there is no FC (Final copy)
NM
EX
HO
HR
FM
TO
DG
SB
SR
IC
FC
LP
SC
DP
RC
--
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
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• External Flag Values
• DP (Drop Packet) Send to Drop FIFO.
• RC (Reclassify Packet) Currently not used.
• NM (No Match) Currently not used.
• EX (Exception Packet) Currently not used.
• HO (Header Only) Currently not used.
• HR (Header Only Return) Not used in current QM.
  (commented code)
• FM (From LC/SW) This flag is forwarded for the
  drop packets (OUTC use to choose drop FIFO).
• Will not be used anymore
• TO (To LC/SW) If 1 send to line card QM.
• Will not be used anymore
• Internal Flag Values
• DG (DataGram) Currently not used.
• SB (SPC-Bound)Set to 1 for SPC bound packet
• SR (SPC-Return) If 1 means that the packet is
  coming from SPC, increment QID by 128
• IC (Initial Copy) IF (copycount / "00" and
  IC_flag 1) need common reference pointer
• FC (Final Copy) Currently not used.
• LP (LFS Option) ??
• SC (Single-Chunk) Forwarded to OUTC for drop
  packets but currently not used by OUTC

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New CARL QM Interface

• CRL ? QM
• Plugin Bit (1b)
• Initial Copy bit (1b)
• This is needed to allocate the common reference
  pointer
• Drop bit (1b)
• CopyCnt(2b)
• Queue Set (OVIN 5b) (3b)
• Will it just be passed through?
• QID(10b)
• PktPtr(20b)
• TotalLength(11b)

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New QM ? OUT

• QM ? OUT
• Plugin Bit (1b) (SB and SR, SR set by ?)
• Free Space Bit (Not of MC 1b) (1b)
• OUT can tell PSM to free memory after retrieving
  packet data.
• PluginFlowIndex (QID) (10b)
• PktPtr (Remains as it is) (20b)
• Output Virtual Interface (OVIN 5b) (3b)

SRAM
QM
OUT
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Verification

• I currently plan to go for full test bench
• 2-3 weeks of effort