COMBINATIONAL LOGIC

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COMBINATIONAL LOGIC
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Combinational vs. Sequential Logic
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Static CMOS Circuit
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NMOS Transistors in Series/Parallel

• Primary inputs drive both gate and source/drain
  terminals
• NMOS switch closes when the gate input is high
• Remember - NMOS transistors pass a strong 0 but a
  weak 1

A
B
X Y if A and B
X
Y
A
X Y if A or B
B
X
Y
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PMOS Transistors in Series/Parallel

• Primary inputs drive both gate and source/drain
  terminals
• PMOS switch closes when the gate input is low
• Remember - PMOS transistors pass a strong 1 but a
  weak 0

A
B
X Y if A and B A B
X
Y
A
X Y if A or B A ? B
B
X
Y
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Threshold Drops
VDD
VDD
PUN
S
D
VDD
D
S
0 ? VDD
0 ? VDD - VTn
VGS
VDD ? 0
PDN
VDD ? VTp
VGS
S
D
VDD
S
D
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Static CMOS
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Example Gate NAND
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Example Gate NOR
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Example Gate COMPLEX CMOS GATE
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Complex Gate Synthesis

• Pulldown networks
• series-connected transistors or subnetworks
  implement AND functions
• parallel transistors or subnetworks implement OR
  functions
• Pullup networks
• series-connected transistors or subnetworks
  implement OR functions
• parallel transistors or subnetworks implement AND
  functions
• Can be designed directly from the logic
  expression the gate is to implement

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FA(BC)

• F NOT(AND(A, OR(BC))
• Pulldown network A(BC)
• AND(A, OR(B, C)) is implemented as
  series-connected a transistor and a subnetwork
  OR(BC)
• OR(BC) is implemented with parallel transistors
  
• Pullup network A(BC)
• AND(A, OR(B, C)) is implemented as parallel
  connection of a transistor and a subnetwork
  OR(B, C)
• OR(B, C) is implemented with series-connected
  transistors

B
A
C
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FA(BC) (contd)
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Complementary CMOS Logic Style Construction
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Properties of Complementary CMOS Gates
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Transistor Sizing
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Propagation Delay Analysis - The Switch Model
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Analysis of Propagation Delay
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Input Pattern Effects on Delay

• Delay is dependent on the pattern of inputs
• Low to high transition
• both inputs go low
• delay is 0.69 Rp/2 CL
• one input goes low
• delay is 0.69 Rp CL
• High to low transition
• both inputs go high
• delay is 0.69 2Rn CL

Rn
B
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Delay Dependence on Input Patterns
AB1?0
A1 ?0, B1
A1, B1?0
Voltage V
time ps
NMOS 0.5?m/0.25 ?m PMOS 0.75?m/0.25 ?m CL
100 fF
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Design for Worst Case
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tp as a function of Fan-In
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tp as a function of Fan-Out
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Influence of Fan-In and Fan-Out on Delay