Verilog HDL

1
Verilog HDL
By Theerayod Wiangtong Electronic Department,
Mahanakorn University of Technology
2
Outline

• ??????????? Hardware Description Language
• ???????????????????????? Verilog
• ???????????????????????????? Verilog
• ????????????????? Verilog
• ?????????????????

3
????????????????????????

• Boolean gt Sum of product gt Gate
• Schematic gt Graphical representation
• HDL gt Language representation
• Structural
• Behavioral

4
??????????????????????????

• ??????????????????????????????????????????????????
  ??????????? ? ???? ??? ????????
  ???????????????????? ?????????????????????????????
  ??????????????????????????????????????? (System
  specification) ??????
• ??????????????????????????????????????????
  ???????????
• ??????????????????????????????????????????????????
  ???????????????? ???????? Schematic
  ?????????????????????????????
• ????????????????????????????????????????????

5
????????????? (Hardware Description Language)

• ????????????? ????????????????????????????????????
  ???????????????
• ???? HDL ??????????????????? ?????????? FSM
  ?????????? Sequential logic ???
  ????????????????????????????? (Truth table)
  ?????????? Combinational logic ???
• ???? HDL ?????????????????????????????????????????
  ??????? Complex PLD (CPLD) ??? Field programmable
  gate array (FPGA) ???????????????? VHDL ???
  Verilog

6
??????? Verilog HDL

• Verilog HDL ??????????????????????????????????????
  ????????????? ???????????????????????????????? ??
  1984-1985 ??? Philip Moorby ?????????????????????
  ???????????????????????????????????????????????
  ?????????????? ????????????????
  ???????????????????????
• ????????? ?? 1990 ????????? ??? Cadence
  ?????????????????????????????????????????
  ????????????????????????????????????
  ??????????????? ??????????? ??????????????????????
  ?????????? IEEE ???? ?? 1995 (IEEE Standard 1364)

7
???????????????????? Verilog

• Universal ???? Verilog ??????????????????????????
  ??????????????????????????????????? (Design
  environment) ???????? ????????????? ????????????
  ????????????? ?????????????
• Extensibility ??????? IEEE std 1364 ??????????
  Verilog PLI (Programming Language Interface)
  ????????????????????????????? Verilog
  ????????????????????????????????????????????????
  ? ?????? ???????????????????????? ???????
• Industrial support ??????????????????? EE Times
  ??????????????????????????????? Verilog
  ??????????? ASIC ???? 1993 ????????? 85
  ???????????????????

8
Verilog ?????????????? VHDL
9
Outline

• ??????????? Hardware Description Language
• ???????????????????????? Verilog
• ???????????????????????????? Verilog
• ????????????????? Verilog
• ?????????????????

10
???????????? Verilog

• ??????????????? (System specification)
  ???????????????????????????????? (Elements) ????
  ? ?????? ????????????????????????????????? ??????
  Verilog ??????? ???????????????????????????
  module ????????? endmodule ????????????

11
Interface ??? Body ????? Verilog module

• module ???????????????????????????????????
  ??????? Body ??? Interface
• Interface ??????????????? ???????????????????????
  ??????????
• Body ?????????????????????????????????
• Optional add-on ???????????????????????????
  ??????????????????????????? ? ????????????????????
  ??? ?????????????? ???????????? 'include

12
???? Interface ???????

• Port list ?????????????????????????????????????
  ????????????????????????????????????????
  ???????????????? Comma (,) ???????????????? ?
• Port declaration ????????????????????????????????
  ?????????????????????? ? ????????? Port list
  ?????????????????????????????????????
  ???????????? ??????????? ????????????????????
  ???????

13
????????????????? Body

• Structural design ???????????????????????????????
  ??????????????? ??????????????? Primitives
  ???????????? ? ????????????????? (Structure)
  ???????????????? ??????????????????????
• Dataflow style ??????????????????????????????????
  ????????????????? ???????????????????
  ???????????????? ? ???????????????????????????????
  ? (Data flow) ??????????????????????????????????
• Behavioral style ??????????????????????????
  (Behavior) ????????????????

14
MUX in structural design style
15
MUX in dataflow design style
16
MUX in behavioral design style
17
?????? (Signal) ?? Verilog

• ???????????????????????????????????????????
  ????????????????????????? ????????????????????????
  ??????????
• ????????????????????????? ? ?????????
  ??????????????????????????????????????????????????
  ???????????? ????????????? ? ?????????????????????
  ??????????????????????????????????????????
  ??????????? ?????? ?????????????
  ?????????????????????????????/????????

18
???(????????????) ?????????

• 0 ???????????????? (Logic zero) ????????????
  (Logic low) ????????????????? (False condition)
  ?????????????????
• 1 ???????????????? (Logic one) ????????????
  (Logic high) ?????????????????? (True condition)
  ?????????????????
• x ???? X ??????????????????? (Logic unknown)
  ??????????????????????????? (Conflict)
  ??????????????? ? ??????????????????????? 0 1
  Z
• z ???? Z ?????????????????????????????? (Open
  circuit) ?????????????? High impedance ? ???????
  ?

19
??????????????? Net

• Nets ?????????????????????????????? ? ???????
  ???????????????? (Storage) ??????????????????
• ????????????? nets ????????????????? (Driver)
  ????????????? (Source) ???????????????????????????
  ????? nets ????????????? High impedance Z
  (??????????????????????? ? ) ??????????? nets

20
??????????????? Net

• ???????? ? ??? nets
• wire ??? tri ???? nets ??????????????????
• wand/triand ??? wor/trior ???? nets
  ????????????????????? And ???? Or ????????
• supply0, supply1, tri0, tri1, trireg ???? nets
  ??????????????????????????????????????????????????
  ?

21
??????????????? Reg

• Registers ??????? nets ???????????????????????????
  ? ????????????????????????????????????????
• ???????????? registers ????????????????????
  ???????????? (Flip-flop) ?????????????????????????
  ??? ????????????????????????????????????????????
  (Clock) ????????????

22
????????????????? Net Reg

• module example (a, b, out_wire, out_reg)
• input a,b
• output out_wire,out_reg
• wire out_wire
• reg out_reg
• //body part start here
• assign out_wire a b
• always_at_(a or b)
• out_reg a b
• endmodule

23
????????????????? Net Reg

• //flipflop inference (edge sensitivity)
• module ff_inf (clock,d,q)
• input clock,d
• output q
• reg q
• always_at_(posedge clock) //inferred flipflop
• q 1 d
• endmodule

24
????????????????? Net Reg

• //latch inference (level sensitivity)
• module lat_inf (clock,d,out)
• input clock,d
• output out
• reg out
• always_at_(clock or d) //inferred flipflop
• if (clock)out 1 d
• endmodule

25
??????????????? register or net

• bits ?? register or wire ???????????
• ltstart-bitgt ltend-bitgt
• ex.
• reg 70 A,B
• wire03 dataout
• reg 70 C
• - assignment statement
• initial begin int1
• A 8b01011010
• B A0..3 A4..7,4b0000
• end

26
???????? ????????????????? ??????????????????
??????????????? ?????????

• ??????????????????????????
• ?????????????? ?????????? ????????? ??????????? _
  ???? ???
• ????????????????????????? ???????? a-z ???? A-Z
  ???? _
• ??????????????? ??? ??????? ?????????????????????
  ?
• ????????????????????????????????
  ??????????????????

27
???????????????? Comment

• One-line comment ???????????? //
  ???????????????????? (end-of-line)
• Block comment ?????????????? /
  ??????????????????????????????? /
  ??????????????????????????????????????? ?
  ????????????????????

28
??????????????? ???????????

• ???????????????????? ????????????
  ????????????????? Scalar signal
• ?????????????????? ? ??????????????? ???
  ???????????? (Buses or vectors)
• ????????????????????????????
• ????????????????????????????????????????
  ??????????? ??????????????? (Index) ???? Bus1,
  Bus 53

29
??????(??????)????????

• ?????? Internal ??????????????????????????????????
  ????????? ? ?????????? External
  ???????????????????????????????? ?
  ??????????????????????????????
• ?????? Verilog ???????????????????????????????????
  
• input ?????????????????????????????????
• output ??????????????????????????????????
• inout ??????????????????? ???????????????????????
  ??????? ????????????????????? bi-directional ports

30
???????????????????????????

• module Processor (Clock,Reset,Read_Write,Data,Addr
  ess)
• input Clock
• input Reset
• output Read_Write
• inout 150 Data
• output 190 Address
• .
• endmodule

Port list
Port declaration
31
Expressions

• ???????????? Expressions ???????
  ???????????????????????? Operands ????????????
  Operators ????????????????????????????????? ?
  ??????
• Out (Left operand) operator (Right operand)
• assign Out1 A B C
• assign Out2 A B
• ?????? Verilog ???? Operator ????????????????
  Operands ?????????? 1, 2, ???? 3 ???
  ??????????????????????? ?????????? Operands
  ???????????????? ?????????????????????????????????
  Verilog ?????????????? VHDL

32
??????? Operands

• ?????? Nets ??? Registers ???????????? ?
  ??????????????? Instance names ???????
• ???????? ???? Constant values ????????????????????
  ? Operands ???????? ???? Integer, Real ???????
• ???????????????????? ? ??? ??????????????? Vector
  ????????????????????? Nets ???? Registers
• ?????????????? Operands ??????????????????????????
  ?? (A call to a function)

33
????????????????? (Integer Constants)

• ?????????????? 2 ???????? ? ??? sized ???
  unsized
• - sized number ????????????????????v
• ltsizedgtltbase_formatgtltnumbergt
• - unsized number sized ?????? 32 bit
  ?????????????? base_format ??????????????? ??? 10

34
????????????????? (Real Number)

• ???????????????? 10 ????????????????
• ????????????????????v
• ltmantisagtlte or Eltexpgt
• ex. 32e-4
• 5.2E2
• ?????????????????????????????????????????
  ???????????????????????????????? (Synthesis) ???

35
????????????????????

• 1234
• b1110
• ha3f
• 4b1111
• 8hx
• 12hz
• -8d6
• 12b1100_1011_1101

• -300
• 10_3_602_2
• 4fc
• 8 hff
• 12d-6
• b_1010

36
?????????????????????

• ?????????? ???? ?????????????????????????????
  ???????????? ??????????? ---------
• ex.
• This is string
• Error Setup
• Hello world
• ex.
• good
• bye
• world

37
???????? (Operators)

• ?????? Verilog ???????????????? 32 ???
  ???????????????????????????????????? Operands
  ????????????? ???
• Unary (with one operand),
• Binary (with two operands),
• Ternary (with three operands) ????
• ?????????????????????????????????????
  ??????????????? ? ????????????
• ?????????????????????? (Arithmetic operator)
• ???????????????? (Logical operator)
• ???????????????????????? (Relational operator)

38
?????????????????????? (Arithmetic operator)

• ?????? ?????????, ????????, ?????????, /
  ????????? ??? ????????? Modulo
  ??????????????????????????????? (Remainder)
  ?????????????????????????? ?????????
• ??? ?????????? Unary operator ????? Operand
  ???????????????? (???????? ?????? )
• Register ???????????????????????? (Unsigned)
  ????????? Integer ????????????????????????????????
  ??????? ????? (Signed)

39
???????????????????????? (Relational Operators)

• ????????????????????????????????????? ???????
  ???????? ???????????
• Precedence ??? Relational operators ??????????
  Arithmetic operators
• ???????????? ??????????? Operands ????????? x
  ???? z ????????????????????????? x (Unknown)
• ?????????????? Operands ??????????
  ??????????????????????????? 0 ?????????????
  (Left padding)

40
????????????????????????(Equality Operators)

• ??????????????????????????????????????? x ????
  z ???????? Case equality (inequality)
  ?????????????????? ???? !
• ?????????????????? 0 ???? 1
  ?????????????????????????????????????????????

41
??????????????? (Logical Operators)

• Logical operators ???????????????????????
  Operands ?????? ??????????????? ?
  ??????????????????? 1 ??? ???????????????? (1)
  ???? ???? (0) ????????
• Bit-wise operators ??????? Operands
  ????????????????????? ? ????????????????????????
  ??????????
• Reduction operators ???????? Operand
  ???????????????????????????? ?????????????????????
  ???????????????? Operand ?????????????????????????
  ???????????

42
??????????????? (????????)
43
???????????????? ?

• ??????????????? Shift Operators (gtgt, ltlt)
• ???? Y RegA gtgt 5
• ?????????????????????????? (Vector
  Concatenations)
• , ?????????????????????? ? ???????????????????
  ?????? ???????? , (Comma) ????????????????????????
  ?
• ???? Y a, b, c52 , d ???? Y
  4DATA10
• ?????????????????????????? (The Conditional
  Assignment)
• ???? assign Out Sel ? In0 In1

44
Operators in Verilog
Concatenate
Unary !
Arithmetic / -
Logical Shift ltlt gtgt
Relational gt lt gt lt
Equality !
! Binary bit-wise
Binary logical
Condition ?

45
Outline

• ??????????? Hardware Description Language
• ???????????????????????? Verilog
• ???????????????????????????? Verilog
• ????????????????? Verilog
• ?????????????????

46
??????? Verilog (1)

• ??????????????????????? (Hierarchical design)
  ??????????????????????????????????????????????????
  ?????????? ??????????????????????????
• ????????????????????? Verilog ????????????????????
  ??????????????????????????? ?
• ??????????????? ??????????? ??????????????????????
  ?????????????????????????? ???????????????????????
  ???? ????????????
• ????????????????????????????????????
  ??????????????????????????????????????????????????
  ????

47
??????? Verilog (2)

• ?????????????????????????????????????????????
  ??????????????????????????????????? ? ???
  ???????????????????????????????
  ??????????????????????????????????
  ?????????????????????????????? ???????????????????
  ???????????????????? ????????????? 'include
  ????????????????????????????

48
???????????????????????????/???

• ??????????????????????????????????? (Internal
  part) ???????????????????? (External part)
• ?????????????????????? ???????????????????????????
  ??????? net ??? reg ????????????????

49
????????????????????
50
????????????????????????

• ?????????????????????????
• Hexagon MyMod (A, B, C)
• ????????????????????????
• Hexagon MyMod (.In1(B), .In2(C), .Out1(A))

51
?????? ????????????? ?? Verilog (1)

• Registers ?????? Verilog ?????????????????????????
  ????????? ? ???????????????? Veriables
  ??????????????????? ???? C ???? Pascal
• reg ???????????????????? ???????? Filp-flop
  ??????????? ??????????????????????????????????????
  ????????? ?????????????? register ?????? x
  (???????????? Nets ??????? z)
• time ?????????????????????????
  ???????????????????????????? (Simulation)
• integer ???????????????????????????????????
  ????????????????????????? ????????????????????????
  ??? ????? ??????????????????????????????????? 32
  ??? (??????? reg ??????????????????)
• real, realtime ??????????????????????????????????
  ? ???????????????????????????????????????
  ?????????????????????????????????? Scientific
  form ??????????????????? ?????? realtime
  ???????????????????????

52
?????? ????????????? ?? Verilog (2)

• ?????? Parameter ?????????????????????????????
• Ex. Module mux2_1 (out,in1,in2,sel)
• .
• parameter bytesize 8
• tphl 8
• tplh 7
• typ_delay (tphl tplh)/2
• wire bytesize 0 in1,in2
• assign typ_delay out sel? In1in2
• .
• endmodule

53
???????? ???????????

• ?????????????? reg ????????????????????????
  (Vector) ???
• ???? reg 70 Data //???????????????? Data
  ?????????????????? 8 ???
• ???????????????????? ?????????????????????????????
  ???????????? reg ?????????????????Instance name
  ????
• reg Data70 //???????????????????????? Data
  ?????????????? 1 ??? ?????????? 8 ???????
• reg 70 MyMem 30 //???????????????? MyMem
  ??????????? 8 ????????????? 4 ???????

54
??????????????????????????????????????
55
???????????????????? ?? Verilog

• ??????????????????????????????????????????????????
  ???????
• ?????????????????? parameter
• ??????????????????
• ??????????????????????????????????????????????
  
• ??????????? (Semi colon) ?????????????????

56
Design styles

• ?????????????????????? ??????????????????????????
  ????????????? 3 ??????????? ? ????????????????????
  ????????????????? ??????
• Structural design
• Dataflow style
• Behavioral style

57
Structural Design

• ??????????????????????????? ??? ?
  ??????????????????????? ? ?????
  ??????????????????????????????????????????????????
  ??????????????? ????????????????? ?
  ????????????????????????????? ????????????????????
  ???????????????? Hierarchy ????????????????????
• Structural Design ????????????????????????? Body
  ??????????????????????????????????????????????????
  ? ? ??????????????? ??????????????????
  (Primitive) ???? ? ???????????????????????????????
  ?????????? ???? ???????????? ? ???????????????????
  ???????????????? UDP (User defined primitive)
  ?????????????????????????? nets ????????????????

58
?????????????????????????

• Multiple-input gates ?????????? 6
  ?????????????????? and, nand, or, nor, xor, ???
  xnor
• Multiple-output gates ?????? buf ??? not
  ????????????????????? ? ???????? ??????????????
• Tri-state gates ?????? bufif0, bufif1, notif0,
  notif1

59
?????????????????????????????

• 1-bit full adder
• ???????????????? wire ?????????? ? ??????
• ????????? ????????????????????????????????????????
  ??????????

60
????????????????????????
??????????????????????? ??????????????????????????
??????????????????? ? ??? ????????????????????????
????????????????????????? ?????????? ? ?????
?????????????????????????????? ????????
61
Dataflow Design

• Continuous assignment ????????????????????????
  driving ????????? nets
• ???????????????????????????????????????????
  ???? Combinational Logic ???????????????
  Continuous assignment ??? ?????? gate
  ???????????????????? nets

62
Examples
wire A, B, C -- reg A, B, C wire 30
V assign A B C assign V30 A -
B assign sum A B cin assign cout (AB)
(Bcin) (Acin) assign 5 out cd
63
??????????? net reg

• module LAT1 (clock , d , out)
• input clock , d
• output out
• reg out
• always _at_ ( clock or d)
• if (clock) out 1 d
• endmodule

64
??????????????????? ?????? assign
assign out enable ? In bz
65
Example
module mux4_1 (out , in1 , in2 , in3 , in4
, sel) input 30 in1 , in2 , in3 ,in 4
output 30 out input 10 sel
wire 30 out assign out (sel
2b00)? In1 (sel
2b01)? In2 (sel
2b10)? In3 (sel
2b11)? In4 4bx endmodule
66
Behavioral Design

• ?????????????????????????????????????? ????
  Dataflow style ?????????????? ? ??????
  ????????????????????????????????????????
• ??????????????????????????????????????????
  ????????????????????????????????? (Behavioral
  description) ????????????? ???????????????????????
  ???????
• ????????????????????????????????? Behavioral
  style ?????????????????????????????????
  ???????????? ?????????????????? if-then-else,
  case statement ???????

67
??? dataflow ??? behavioral
initial block ????????????????????????????????????
????????? (time 0) ???????????????????????????????
???? always block ???????????????????????????????
? 0 ????????? ?????????????????? ? ????????????
(Infinite loop)
68
????????????
???????????????? Blocks ???????????? ? ???
???????????????????????? ?????????????????????????
??????????????? ?????????????????????????????
Blocks ???????? ? ??? ??????
69
??????????????????????????????? Procedural
Assignment

• Procedural assignment ?????????????? Continuous
  assignment ???????????
• ?????????? assign ???????????????
• ?????????????? Behavioral block (initial or
  always)
• ?????????????? (???????) ???????? reg ????
• Procedural assignment ?? always
  ??????????????????????????????????????????????????
  ???????????????????? Sensitivity list
  ??????????????? always (????????????????? assign)

70
If-then-else Operation

• ?????????????????????????? ???????????????????????
  ?????????????? ????????????????? ???????????
  Conditional operations

71
Case Operation

• ??????????????????????? ? ??????? ?
  ???????????????? if-else-if ???????????????????
  ??????????????????????? ??????????????????????????
  ????????????????????????? ??????????????????????
  ? ???????? ??????????????? case

72
Loop Operation

• ???? Verilog ?????????????????????????????????
  forever, repeat, while ??? for ???????????????????
  ???????????????? ??????????????????????????????
• forever ??????????????????????????????????????
• repeat ??????????????????????????????????????
  ??????????????????????????????????????
• while ???????????????????????????????????????????
  ?????? ???????????????????????????
  ??????????????????????????????????????????????????
  ????
• for ????????????????????????????????
  ?????????????????????????? ???????????????????????
  ???????????????? ?????????????????
  ????????????????????????????????????????????????

73
?????????????? For-loop

• ?????????????? for-loop ?????????????????????????
  ????????????????????????????? ???????????????
  4-bit full adder

74
Mix and Match Assignment

• ?????????????????????????????? Procedural ???
  Continuous assignment ????????????????????????????
  ?

75
??????????????? Timing

• ??????????????? ????????? Timing ??????
  3?????????
• Delays ?????? ????????????
• ex. 10 b a
  
• b 20 a
• Events ?????? ????????????
• ex. _at_ (clock) qd
• _at_(posedge clock ) q d
• _at_(negedge clock) q d
• _at_( a or b ) c a b
• waits ??? wait ????????????ex.
• wait (! Ena) 20 out data

76
???????? Task

• ????????????????????? Procedures ???? ? ??
  module ????????
• Task ????????????????? ???
• task task_name
• //declarations
• //statement
• endtask
• ??????????? procedure task
• task_name (I/O arguments)

77
???????? Function

• ????????????????????? Procedures ???? ? ??
  module ????????
• Function ????????????????? ???
• function range_or_type function_name
• //declarations
• //statement
• endfunction
• ??????????? procedure function
• function_name (input arguments)

78
Outline

• ??????????? Hardware Description Language
• ???????????????????????? Verilog
• ???????????????????????????? Verilog
• ????????????????? Verilog

79
?????????????????????????????
80
??????????????????????

• ?? latch ???????????????????
• ????????????????????????????????????? 11
  ????????
• ????????????????????????????????????
  ???????????????????? (latch) ??????????

81
???????????????????????????????
82
???????????? Sensitivity list (1)

• ??????????? always ???????????????????????????????
  ???????? ? ?????????????? begin ??? end ?? always
  block ??????? ????????????????????? Sensitivity
  list ?????????????????? ??? always block
  ????????????????? ??????????????????????
• ?????????????????????????????????? ? ????????????
  (?????? or ???????????)
• ?????????????????????????????????????????????????
  (edge trigger signal posedge, negedge)
  ?????????????? (level trigger signal)???

83
???????????? Sensitivity list (2)
84
???????????? Sensitivity list (3)

• ??????????????????????????????????
  ????????????????????????????

85
?????????????????????????????
86
Blocking ??? Non-blocking Assignment

• Non-blocking assignment lt
• Blocking assignment
• ??????????? always block ??????????? Blocking ???
  Non-blocking assignment ???????????? Blocking
  assignment ??????? Update ???????????????????????
  ??? Non-blocking ??? Update ??????????????????????
  ???????????? ? ??????????????????? end

87
??????????????? Sequential logic
?????? Non-blocking assignment ??????????????
Sequential logic ?? always block
88
??????????????? Combinational logic
?????? Blocking assignment ??????????????
Sequential logic ?? always block
89
Priority Logic
90
???????????????????????????
91
??????????????????????
92
Outline

• ??????????? Hardware Description Language
• ???????????????????????? Verilog
• ???????????????????????????? Verilog
• ????????????????? Verilog
• ?????????????????

93
(No Transcript)
94
????????????????? 32-bit ALU
95
???????????????????????
96
?????????????????????????????????