Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns

1
Sequential Circuit BIST Synthesis using Spectrum
and Noise from ATPG Patterns

• Nitin Yogi and Vishwani D. Agrawal
• Auburn University
• Auburn, Alabama 36849, USA

2
Outline

• Specifying a BIST problem
• Proposed method
• Spectral Analysis
• BIST implementation
• Results
• Fault Coverage
• Area Overhead
• Conclusion

3
Two Types of BIST methods

• Scan-based testing
• Advantages
• High fault coverage
• Disadvantages
• Area delay overhead, yield loss, large vector
  size and testing times
• Non-scan based testing
• Advantages
• Disadvantages of scan-based testing eliminated
• Disadvantages
• Requires sequential ATPG
• High test generation complexity and low fault
  coverages
• Alleviated using DFT schemes
• Sequential ATPG-like vector generation in BIST
  environment

Problem definition
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Proposed Method

• Step 1 Spectral analysis
• Sequential vectors (ATPG or any other type)
  analyzed in the spectral domain
• Significant spectral components chosen for BIST
  implementation
• Step 2 BIST implementation
• Hardware synthesis of significant spectral
  components to generate ATPG-like vectors

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Test vectors and bit-streams
Sequential Circuit (CUT)
Outputs
Input 3
Input 5
Input J
Input 1
Input 2
Input 4
. . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . .
Vector 1 ? Vector 2 ? Vector 3 ? Vector 4
? Vector 5 ?
A bit-stream
Time
. . . . .
. . . . .
. .
. . . . . . . . . . .
. . . .
Vector K ?
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Spectral Characterization of a Bit-Stream
w0

• Walsh functions a complete orthogonal set of
  basis functions that can represent any arbitrary
  bit-stream
• Walsh functions form the rows of a Hadamard
  matrix

w1
w2
w3
1 1 1 1 1 1 1 1 1 -1 1 -1 1 -1 1 -1 1
1 -1 -1 1 1 -1 -1 1 -1 -1 1 1 -1 -1 1 1 1
1 1 -1 -1 -1 -1 1 -1 1 -1 -1 1 -1 1 1 1 -1
-1 -1 -1 1 1 1 -1 -1 1 -1 1 1 -1
H8
Walsh functions (order 8)
w4
w5
w6
w7
Example of Hadamard matrix of order 8
time
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Analyzing Bit-Streams of ATPG vectors
Input 1 Input 2 . . .
Set 1
Vector 1 Vector 2 . . .
Spectral coeffs.
Bit stream
Spectral Analysis
0s to -1s
Set j
Time
. . . . . . . .
. .
C(2,1) input 2 set 1
input 2 set 1
Sets of bit-streams of Input 2
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Determining Significant Components
For input i
Averaged Spectrums
. . . .
Set J
Set 1
Averaging
Component Spectrum
. . . .
Phases of significant components
Averaging
Power Spectrum
. . . .
M significant components chosen
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Input Vector Holding

• Hold input vectors constant while applying system
  clock.
• Holding length related to sequential depth.
• Sequential depth Maximum number of FFs on any
  path between PI and PO.
• Holding a vector constant for number of clock
  cycles equal to sequential depth propagates a
  fault through the activated sequential path1.
• Holding maps combinational ATPG onto acyclic
  sequential circuit 2.
• However, all testable combinational ATPG faults
  not detected by holding 3.

1 L. Nachman, K. Saluja, S. Upadyaya, and R.
Reuse, Random Pattern Testing for Sequential
Circuits Revisited, in Proc. Fault-Tolerant
Computing Symp., pp. 4452, June 1996. 2 H. B.
Min and W. A. Rogers, A Test Methodology for
Finite State Machines using Partial Scan Design,
J. Electronic Testing Theory and Applications,
vol. 3, no. 2, pp. 127137, 1992. 3 Y. C. Kim,
V. D. Agrawal, and K. K. Saluja, "Combinational
Automatic Test Pattern Generation for Acyclic
Sequential Circuits," IEEE Transactions on
Computer-Aided Design of Integrated Circuits and
Systems, vol. 24, no.6, pp. 948-956, June 2005.
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Holding and Weighted Random Patterns
Circuit Total No. of faults Number of faults detected Number of faults detected Number of faults detected Number of faults detected
Circuit Total No. of faults 64k random vectors 64k random vectors 64k weighted random vectors 64k weighted random vectors
Circuit Total No. of faults Without holding With holding Without holding With holding
s298 308 269 273 273 273
s820 850 414 449 744 764
s1423 1515 891 1217 1449 1469
s1488 1486 1161 1369 1443 1443
s5378 4603 3222 3424 3288 3537
s9234 6927 1268 1305 1293 1303
s15850 13863 5249 6270 5847 6696
s38417 31180 4087 4185 4803 4949
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BIST Architecture
M-bit counter divides system clock frequency
repeatedly by 2 and generates BIST clock
System clock
To CUT
Clock divider and holding circuit
Cellular Automata Register with AND-OR gates
N-bit counter with XOR gates
BIST clock
Weighted pseudo-random pattern generator
Hadamard wave generator
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Spectral component synthesizer
Input 1
System clock
3
To CUT
BIST clock
1
Input 2
Randomizer
1
Hadamard Components
Input 3
1
Weighted pseudo-random bit-streams
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Hadamard BIST Results
Circuit Total No. of faults Number of faults detected Number of faults detected Number of faults detected Number of faults detected Number of faults detected
Circuit Total No. of faults FlexTestATPG 64k random vectors 64k weighted random vectors Hadamard BIST (64k vectors) Haar BIST1 (64k vectors)
s298 308 273 273 273 273 273
s820 850 793 449 764 777 710
s1423 1515 1443 1217 1469 1468 1468
s1488 1486 1446 1369 1443 1443 1441
s5378 4603 3547 3424 3537 3603 3609
s9234 6927 1588 1305 1303 1729 1413
s15850 13863 7323 6270 6696 6844 5888
s38417 31180 15472 4185 4949 17020 4244
1. S. K. Devanathan and M. L. Bushnell, Test
Pattern Generation Using Modulation by Haar
Wavelets and Correlation for Sequential BIST, in
Proc. 20th International Conf. VLSI Design, 2007,
pp. 485491.
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Hadamard BIST Results
Circuit Total No. of faults Number of faults detected Number of faults detected Number of faults detected Number of faults detected Number of faults detected
Circuit Total No. of faults FlexTestATPG 64k random vectors 64k weighted random vectors Hadamard BIST (64k vectors) Haar BIST1 (64k vectors)
s298 308 273 273 273 273 273
s820 850 793 449 764 777 710
s1423 1515 1443 1217 1469 1468 1468
s1488 1486 1446 1369 1443 1443 1441
s5378 4603 3547 3424 3537 3603 3609
s9234 6927 1588 1305 1303 1729 1413
s15850 13863 7323 6270 6696 6844 5888
s38417 31180 15472 4185 4949 17020 4244
Maximum faults detected in 6 / 8 circuits
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Longer BIST Sequences
Circuit FlexTest FlexTest Hadamard BIST Hadamard BIST Hadamard BIST
Circuit Fault coverage () No. of vectors Fault coverage () at 64K vectors Fault coverage () at 128K vectors BIST vecs. for FlexTest ATPG cov.
s298 88.64 153 88.64 88.64 757
s820 93.29 1127 91.41 91.88 (!)
s1423 95.25 3882 96.90 96.90 22345
s1488 97.31 736 97.11 97.11 (!)
s5378 77.06 739 78.27 78.67 8984
s9234 22.92 15528 24.96 25.25 8835
s15850 52.82 61687 49.37 52.15 198061
s38417 49.62 55110 54.59 63.07 43240
ATPG fault coverage achieved in 6 / 8 circuits
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Area Overhead
Circuit No. of transistors in circuit Hadamard BIST Hadamard BIST Haar BIST1 Haar BIST1
Circuit No. of transistors in circuit No. of transistors Area overhead No. of transistors Area overhead
s298 890 908 102.02 834 93.71
s820 1896 1472 77.64 1612 85.02
s1423 4624 1637 35.40 1555 33.63
s1488 4006 1069 26.68 1078 26.91
s5378 12840 2342 18.24 2487 19.37
s9234 23356 2700 11.56 2552 10.93
s15850 43696 4908 11.23 4595 10.52
s38417 108808 3606 3.31 2135 1.96
Approximately similar area overheads
1. S. K. Devanathan and M. L. Bushnell, Test
Pattern Generation Using Modulation by Haar
Wavelets and Correlation for Sequential BIST, in
Proc. 20th International Conf. VLSI Design, 2007,
pp. 485491.
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Conclusion

• Proposed a novel method for test generation for
  sequential circuit BIST
• Proposed unique circuits for mixing spectral
  components and noise
• Method detects equal or more faults than ATPG
  vectors in 6 out of 8 ISCAS89 benchmark circuits
• Moderate area overhead compared to existing
  methods
• Proposed method is flexible and adaptable
• Any other suitable vectors can be used instead of
  ATPG vectors.
• Any compatible transform for binary bit-streams
  can be used for spectral analysis instead of
  Hadamard transform.
• BIST coverage limited by coverage of ATPG vectors
• DFT for sequential circuits to improve ATPG
  coverage

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Thank You!Any questions please ?