Designing fast analog memories for precise time measurement D.Breton (LAL Orsay)

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Designing fast analog memories for precise time
measurement D.Breton (LAL Orsay)
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Introduction

• The technologies have evolved at an amazing rate
  in the last decade, and during this period our
  electronics engineer everyday work has been
  transformed consequently
• Sometimes we have to build systems housing only
  few channels, but more often a lot, thus pushing
  us to look for the best solution to perform as
  precise as possible signal measurements at the
  lowest cost and power consumption, in order to be
  able to build large scale systems
• Our consecutive developments thus made us use
  high-end commercial ADCs and TDCs as well as
  developing high performance analog memories
• Now we deal with GS/s, which actually permits
  getting closer to ps
• gt we can build high-end TDCs using waveform
  digitization

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About TDCs

• Existing electronics for time measurement is
  mostly based on Time to Digital Converters (TDC).
  
• A TDC converts the arrival time of a binary
  signal into digital value.
• It is characterized by
• Its time step and its main clock frequency
• Its effective resolution (which can be very
  different from time step)
• Its dead-time and its mean maximum hit rate
• Its number of channels
• Very few high-end products on the market, mostly
  dedicated to LHC
• HPTDC from CERN gt 25ps 40MHz
• TDC-GPX from ACAM gt 8 channels, 80ps 40MHz
• There is an important demand for time of flight
• measurement in the medical community, and now for
  ps
• precision in high energy physics

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State of the art for TDCs

• TDC with voltage ramp
• gt best solution for precision
• Time resolution 10 ps
• Usually used with a Wilkinson ADC for power and
  simplicity reasons
• gt limited by dead time which can be a problem
  for high rate experiments
• TDC with digital counters and Delay Line Loops
  (DLL)
• gt advantage produces directly the encoded
• digital value but limited by delay line step
• - Time resolution of todays most advanced ASICs
  25 ps

• BUT a TDC needs a binary input signal
• analog input signal has to be translated to
  digital with a discriminator
• overall timing resolution is given by the
  quadratic sum of the discrimator and TDC timing
  resolutions

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New TDC developments

• There are very few new developments in the high
  precision TDC area
• University of Alberta worked on using the HPTDC
  at 80MHz and achieved 15ps of resolution using
  custom CFDs
• CERN envisaged a new DLL-based TDC targetting 15
  ps of resolution
• Anyhow, the standard DLL-based option is limited
  by the time propagation step in the DLL and the
  fact that one cannot interpolate this information
• Usual trick for improving the precision
  interleaving DLLs fed with phase shifted signals
• Only way to further increase the precision is to
  run for smaller technologies
• But single delay step will hardly go below a few
  10 ps
• And if one wants to keep reasonable clock
  frequencies in the chips (used for rough time
  counters), DLLs will remain long gt bad for
  precision

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ADC and TDC

• The best way to precisely measure the arrival
  time of a signal is to digitize it with a very
  fast and precise ADC.
• Indeed, once data is digitized, one can perform a
  digital treatment of data to precisely extract
  time information
• Waveform contains all information (if properly
  digitized)
• Depending on the information requested
  (amplitude, charge, time, FFT, ), different
  types of algorithms can be used
• Goal is to find the both simplest and most
  effective algorithms which can be integrated
  within companion FPGAs
• Waveform sampling can be used for designing high
  performance TDCs
• It was shown that 5-10GS/s sampling rate together
  with a good SNR (gt10bits) was leading way to the
  ps level
• Signal to noise ratio is always an issue, even
  for a TDC

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Extracting the time from the signal CFD

• The easiest way to extract the time information
  from a digitized signal is to perform a digital
  Constant Fraction Discrimination (CFD)
• Indeed, a simple threshold method introduces Time
  Walk which depends on the signal amplitude
• in order to remove the time walk, threshold has
  to be set as a constant fraction of the signal
  amplitude
• Algorithm can be as simple as looking for the
  closest sample to the peak and performing a
  linear interpolation between samples around the
  threshold gt easy to implement within a FPGA.
• More complex algorithms based on multi-sample
  digital filtering may improve the resolution

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Jitter induced by electronics noise
Simplified approach
slope 2?Af3db tr 1/(3 f3db)
Zoom
Jitter ps NoisemV / Signal Slope mV/ps
tr / SNR Ex the slope of a 100mV - 500MHz
sinewave gets a jitter of 2ps rms from a noise
of 0.6mV rms

• Conclusions
• The higher the SNR, the better for the
  measurement
• A higher bandwidth favours a higher precision
  (goes with its square root).
• But for a given signal, it is necessary to
  adapt the bandwidth of the measurement system to
  that of the signal in order to keep the
  noise-correlated jitter as low as possible
• Designs become tricky for ultra fast signals
  with a bandwidth gt 1GHz

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ADC-based TDC

• The best digitizer would be a low-power flash ADC
  running at a rate gtgt GS/s over a lot of bits (12)
• Because every single sample would have followed
  the same path
• Sampled by the physical same clock (thus with an
  excellent jitter performance)
• Digitized by the same elements gt thus avoiding
  any dispersion due to layout non-uniformities
• This doesnt exist
• gt very fast ADCs are based on a bank of
  parallel ADCs
• gt they require an internal complex calibration
• gt they consume quite a lot of power
• The output dataflow of these circuits makes them
  very difficult to use
• The most powerful products on the market
• 8bits gt 3GS/s, 1,9 W gt 24Gbits/s,
• 10 bits gt 3GS/s, 3,6 W gt 30Gbits/s
• 12 bits gt 3,6GS/s, 4,1 W gt 43,2Gbits/s
• 14 bits gt 400MS/s, 2,5 W gt 5,6Gbits/s

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An actual 12 bits and 3.6GS/s
BGA 292 pins Output links 24 x1,8Gbits/s
1.8 GHz !

• Need of a VERY high-end FPGA
• power, cost, board design complexity,
• and what about radiation if any ?

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Why Analog Memories ?

• Analog memories actually look like perfect
  candidates for high precision time measurements
  at high scale
• Like ADCs they catch the signal waveform (this
  can also be very useful for debug)
• There is no need for precise discriminators
• TDC is built-in (position in the memory gives the
  time)
• Only the useful information is digitized (vs
  ADCs) gt low power
• Any type of digital processing can be used
• Only a few samples/hit can be read gt this may
  limit the dead time
• Simultaneous write/read operation is feasible,
  which may further reduces the dead time if
  necessary
• Main difficulty is less sampling frequency than
  signal bandwidth
• But their design is tricky if one wants to reach
  the necessary level of performance.

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Basic principles of circular analog memory

• A write pulse is running along a folded delay
  line.
• Sampling stops upon trigger.
• Readout can target an area of interest
• Starting from Trigger cell (marked during signal
  
• recording) - programmable offset (linked to
  latency).
• Total readout can however be necessary.
• Read Cell index necessary.
• Dead time due to readout has to remain as small
  as
• possible (lt100ns / sample).

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Main design options

• The choices of architectures are different
  depending on the recording options.
• Main options
• Pure waveform recording (can cover a long time
  period)
• gt can be used for rough time measurement.
• Precise time measurements.
• It looks like both are not achievable with the
  same designs
• The ps level relies on the quality of the
  sampling then in the capacity to easily correct
  the remaining fixed sampling errors
• Of course the better original sampling, the
  easier
• The calibration has to remain reasonable, as well
  as necessary correction of data

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Different types of implementation
SAM
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Targetting the ps

• As said before, a perfect digitizer would be for
  instance a 10GS/s 12-bit flash ADC.
• But 10GS/s sampling doesnt give enough time to
  work on the sampled signal (100ps for sampling
  transfer )
• Moreover, the 120Gbits/s output data rate could
  make anybody nauseous
• the idea is to keep the high sampling rate and to
  increase the time for processing the samples by
  parallelizing the operation via the Sampling
  Delay Line
• There will be as many sample and hold cells as
  delays in the line
• This increases the time allowed for sampling the
  signal (write pulse can cover many consecutive
  delay cells)

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Basic scheme
Pros very simple and easy to implement
scheme Cons time propagation is not servo
controlled gt individual delays have to be
calibrated and may vary with time and temperature
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Time Non_Linearities

• Dispersion of single delays gt time DNL
• Cumulative effect gt time INL. Gets worse with
  delay line length.
• Systematic fixed effect gt non equidistant
  samples gt Time Base Distortion
• If we can measure it gt we can
  correct it !
• But calibration and even more correction have to
  remain reasonable.

In a Matrix system, DNL is mainly due to signal
splitting into lines gt modulo 16 pattern if 16
lines
Remark same type of problem occurs with
interleaved ADCs
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Improved scheme
Here, time propagation is servo controlled gt
individual delays are much more precise and
should not vary with time. However, if the Delay
Line is too long, integral non linearity may be
important
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How to use it ?
Here, output rate input rate gt this actually
is an ADC ! Actually, most ADCs integrated in
high-end oscilloscopes front-end work that way !
Fclock/Nb of delays
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Dual-stage analog memory
Here, output rate input rate only for the first
stage Difficulty is to copy the sampled signal
very properly between the two stages Short first
stage is fixing the time precision performance
but transfer may damage the information
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Towards a ps TDC

• In order to build a real TDC targetting the ps
  level, adding an analog memory to a usual DLL TDC
  permits relieving the walk constraint on the
  discriminator and improving the time precision by
  an order of magnitude
• Here the Delay Line is servo-controlled and can
  be as short as the signal to measure gt very good
  time resolution can be envisaged

Critical path for time measurement
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Remarks

• The technology choice depends on the design.
• It might be good not to chose too complex or
  expensive technology if this is not necessary
• Following the trends might be risky
• There are many cheap and good old technologies
• An important element is the channel occupancy
• The architecture has to be adapted to the
  required channel hit rate
• Waveform sampling means that a certain amount of
  cells has to be readout for each hit
  reconstruction
• gt Intrinsic deadtime
• If the readout scheme becomes too difficult to
  implement, reducing the pixel size and increasing
  the number of channels might be a solution
• But then the overall number of channels will
  follow
• gt try to increase the number of channels within
  one chip

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Remarks (2)

• The analog memory could also be used as a first
  level derandomizer
• Either individual cells or banks of cells could
  be frozen waiting for readout while sampling goes
  on
• This implies a simultaneous write/read operation
  in the memory
• potential source of crosstalk, noise, distorsion
  
• critical design
• but if the derandomizer depth is sufficient, the
  memory could get close to zero deadtime
• When the ps is the goal, the clock distribution
  becomes a problem by itself, especially for high
  scale systems
• The board design also becomes really difficult,
  mixing high bandwidth analog front-end and fast
  digital logics

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Memory-associated ADC

• Sampled analog waveform has to be digitized
• ADC can be internal to the chip, or external
• External
• The simplest solution multiplexing all the
  samples towards a single ADC
• Cheap but induces a relatively high dead-time
• The most effective in terms of dead-time driving
  many ADCs in parallel (can be multi-channel ADCs)
• Internal
• The simplest solution the Wilkinson ADC
• Can be parrallelized (ramp and counter can be
  shared)
• Can be partly inside (ramp and comparator) and
  outside the chip (counter located in the
  companion FPGA)
• Counter can be embedded in each cell
• Smart implementations highly increasing the speed
  can be used (WILKY)
• The main problem with internal ADC extracting
  rapidly the digital data
• gt this could really become problematic for dense
  circuits

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Advanced integrated ADC design WILKY

• New ADC development based on boosted Wilkinson
  architecture.
• Use of DLL-based digital TDC techniques to
  measure the time in a ramp ADC (patented in 2005)
• Equivalent to a Wilkinson ADC with a 3.2 GHz
  clock.
• 4-channel prototype validated in 2006 in CMOS
  0.35µm technology
• Easily expendable to 64 channels or more

Raw Time counter
Fine Time DLL
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Summary

• Waveform sampling can be used for designing high
  performance TDCs
• ADCs would do the job nicely but at least 99 of
  data would go to the bin at owners expense!
  (power, FPGA, )
• Analog memories actually look like perfect
  candidates for high precision time measurement at
  high scale and reasonable trigger rates
• Design has to be adapted for such a requirement
  (short servo-controlled sampling delay lines)
• Not only high sampling precision but high SNR is
  mandatory
• 1GHz of bandwidth currently looks like a
  technical boundary if one wants to keep a low
  signal distorsion
• But this should already permit reaching the ps
  level