MOS Field-Effect

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MOS Field-Effect Transistors (MOSFETs)
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MOSFET ( Voltage Controlled Current Device)

• MOS Metal Oxide Semiconductor
• Physical Structure
• FET Field Effect Transistor
• The current controlled mechanism is based on an
  electric field established by the voltage applied
  to the control terminal GATE
• Uni-polar Current is conducted by only one
  carrier
• IGFET Insulated Gate FET
• CMOSFET Complementary MOSFET
• 1930 was Known, 1960s Commercialized
• 1970s Most commonly used VLSI
• NMOSFET/PMOSFET n/p-channel enhancement mode
  MOSFET

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MOSFET

• Small Size
• Manufacturing process is simple
• Requires comparatively low power
• Implement digital analog functions with a fewer
  resistors very large scale Integrated (VLSI)
  circuit
• Study Includes
• Physical structure
• Operation
• Terminal characteristics
• Circuit Models
• Basic Circuit application

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Figure 4.1 Physical structure of the
enhancement-type NMOS transistor
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Device Structure

• Types n channel enhancement MOSFET
• p channel enhancement MOSFET
• n Channel MOSFET
• Fabricated on a p-type substance that provides
  physical support for the device.
• Two heavily doped n-type region are created
• n Source (S) n for lightly doped n type
  silicon
• n Drain (D) n for heavily doped n type
  silicon
• Area between source Drain
• Thin Layer of Silicon dioxide (SiO2) is grown
  with thicker of tox 2-50 nanometers An
  excellent electrical insulator
• Metal is deposited on top of the oxide layer to
  form the Gate electrode. Metal contact is made to
  Source Drain and the substrate (Body)

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Figure 4.1 Physical structure of the
enhancement-type NMOS transistor
Cross-section. Typically L 0.1 to 3 mm, W
0.2 to 100 mm, and the thickness of the oxide
layer (tox) is in the range of 2 to 50 nm.
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Device Structure

• Four terminals
• Source (S)
• Gate (G)
• Drain (D)
• Body (B)
• L Length of channel region
• W Width of the substrate
• tox Thickener of An oxide Layer

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Device Structure

• Metal oxide semiconductor - name is derived from
  its physical structure
• Insulted Gate FET (IGFET) gate is
  electrically insulated from the device body
• Current in gate terminal is small (10-15 A)
• Substrate forms pn junctions with the source
  drain region is kept reversed biased all the
  time
• Drain will be at a positive voltage relative to
  the source, two junctions are at cutoff mode if
  substrate is connected to the source. Thus Body
  will have no effect on operation of the device.

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Principle of operation

• Voltage applied to the Gate controls current flow
  between Source Drain with direction from Drain
  to Source in channel region
• It is a symmetrical device thus Drain Source
  can be interchanged with no change in devices
  characteristics
• With no bias gate voltage, two back-to-back
  diodes exist in series between drain and source.
• No current flows even if vDS is applied. In fact
  the path between Source Drain (1012?) has very
  high resistance

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Figure 4.2 The enhancement-type NMOS transistor
with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
beneath the gate.
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Creating a Channel for Current Flow

• Source Drain are grounded and a positive
  voltage (vGS) is applied to the gate.
• Holes are repelled-leaving behind a carrier
  depletion-region.
• Depletion region is populated with the bounded
  negative charges associated with the acceptor
  atoms and are uncovered because the neutralizing
  holes have been push downward into the substrate.

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Channel for Current Flow

• Positive gate attracts electrons from the n
  source drain region into the channel region.
• Due to electrons accumulated under the gate, an
  n region is created connects source drain
  region.
• Thus if voltage is applied between source
  drain, current flows due to mobile electrons
  between drain source.
• n region forms a channel n channel MOSET
  (NMOSFET)

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Channel for Current Flow

• An n channel MOSFET is formed in a p type
  substrate. Known as Inversion Layer.
• The value of vGS that causes sufficient number of
  mobile electrons to be accumulate in the channel
  region to form conducting channel is called
  threshold Voltage Vt.
• Vt for n channel is positive value is 0.5
  to 1V

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Channel for Current Flow

• Gate channel region form a parallel plate
  capacitor, with oxide layer as the capacitor
  dielectric.
• Positive charge is accumulated on gate electrode
  negative charge on channel electrode.
• An electric field thus develops in the vertical
  direction.
• Capacitor charge controls the current flow
  through the channel when a voltage vDS is
  applied.
• Gate Channel

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Figure 4.3 An NMOS transistor with vGS gt Vt and
with a small vDS applied.
The device acts as a resistance whose value is
determined by vGS. Specifically, the channel
conductance is proportional to vGS Vt and
thus iD is proportional to (vGS Vt) vDS.
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Applying a Small vDS

• vDS is applied (vDS 50mV) causes iD to flow
  through induced n channel.
• Direction is opposite to that of the flow of
  negative charges.
• Magnitude of iD depends upon density of electrons
  and in term on vGS .
• vGS Vt
• Negligible current iD as the channel has been
  just induced.
• vGS gt Vt
• iD current increases, increases conductance of
  the channel is proportional to Excess gate
  voltage (vGS - Vt )
• vGS - Vt is known as Excess gate Voltage ,
  Effective Voltage Overdrive Voltage (VOV)
• MOSFET operatrates as a linear resistance whose
  value is controlled by vGS.
• vGS above Vt enhances the channel named
  Enhanced Mode operation enhanced type MOSFET
• iD iS, iG 0

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Figure 4.4 The iDvDS characteristics of the
MOSFET
When the voltage applied between drain and
source, vDS, is kept small. The device operates
as a linear resistor whose value is controlled by
vGS.
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Figure 4.5 Operation of the enhancement NMOS
transistor as vDS is increased. The induced
channel acquires a tapered shape, and its
resistance increases as vDS is increased. Here,
vGS is kept constant at a value gt Vt.
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The drain current iD versus the drain-to-source
voltage vDS for an enhancement-type NMOS
transistor operated with vGS gt Vt.
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Increasing vDS causes the channel to acquire a
tapered shape. Eventually, as vDS reaches vGS
Vt the channel is pinched off at the drain end.
Increasing vDS above vGS Vt has little effect
(theoretically, no effect) on the channels shape.
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Derivation of the iDvDS characteristic of the
NMOS transistor.
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Drain Current iD

• Directly Proportional to
• Mobility of Electrons in the channel µn (µm2/V)
• Gate Capacitance per unit gate area Cox (µF/ µm)
• Width of the substrate (µm)
• Gate-Source Voltage vGS (Volts)
• Drain-Source Voltage v DS (Volts)
• Indirectly Proportional to
• Length of the channel (µm)

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iD vDS relationship
Troide Mode
Saturation Mode
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The p Channel MOSFET

• Fabricated on an n-type substrate with p regions
  for Drain Source
• Holes are the current carriers.
• vGS vDS are negative
• Threshold voltage Vt is negative.
• Both NMOS PMOS are utilized in Complementary
  MOS or CMOS circuits

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Complementary MOS or CMOS
Cross-section of a CMOS integrated circuit. Note
that the PMOS transistor is formed in a separate
n-type region, known as an n well. Another
arrangement is also possible in which an n-type
body is used and the n device is formed in a p
well. Not shown are the connections made to the
p-type body and to the n well the latter
functions as the body terminal for the p-channel
device.
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iD vDS Charateristics

• Modes of operation
• Cutoff
• Triode (Saturation in BJT)
• Saturation ( Active in BJT)

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The iDvDS characteristics for a device with kn
(W/L) 1.0 mA/V2.
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The iDvGS characteristic for an enhancement-type
NMOS transistor in saturation (Vt 1 V, kn W/L
1.0 mA/V2).
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Large-signal equivalent-circuit model of an
n-channel MOSFET operating in the saturation
region.
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Finite Output Resistance in Saturation
Increasing vDS beyond vDSsat causes the channel
pinch-off point to move slightly away from the
drain, thus reducing the effective channel length
(by DL).
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Finite Output Resistance in Saturation
Effect of vDS on iD in the saturation region. The
MOSFET parameter VA depends on the process
technology and, for a given process, is
proportional to the channel length L.
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Finite Output Resistance in Saturation
Large-signal equivalent circuit model of the
n-channel MOSFET in saturation, incorporating the
output resistance ro. The output resistance
models the linear dependence of iD on vDS
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Circuit symbol for the p-channel enhancement-type
MOSFET.
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Characteristics of PMOSFETTriode Mode of
Operation
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Characteristics of PMOSFETSatuaration Mode of
Operation
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The Roll of Substrate Body Effect

• Substrate for many Transistors
• Body is connected to the most negative power
  supply to maintain cutoff conditions for all the
  substrates to channel junctions
• Another gate

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Temperature Effects

• Vt and Kn are effected by the temperature
• Vt increases by 2mV per 10C rise in temperature
• Kn decreases with rise in temperature thus drain
  current increases. The effect is dominant. Thus
  ID decreases with increase in temperature
• MOSFET in Power circuits

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Graphical construction to determine the transfer
characteristic of the amplifier in (a).
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Circuit for Example 4.9.
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Biasing the MOSFET using a large drain-to-gate
feedback resistance, RG.
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Biasing the MOSFET using a constant-current source
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Conceptual circuit utilized to study the
operation of the MOSFET as a small-signal
amplifier.
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Recap Transfer Function
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Transfer characteristic showing operation as an
amplifier biased at point Q.
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Conceptual circuit utilized to study the
operation of the MOSFET as a small-signal
amplifier.
The DC BIAS POINT
To Ensure Saturation-region Operation
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Signal Current in Drain Terminal
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Figure 4.35 Small-signal operation of the
enhancement MOSFET amplifier.
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Total instantaneous voltages vGS and vD
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Small-signal p models for the MOSFET
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Common Source amplifier circuit Example 4-10
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Small Signal T Model NMOSFET
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Small Signal Models
T Model
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Single Stage MOS Amplifier
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Amplifiers Configurations
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Common Source Amplifier (CS) Configuration
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Common Source Amplifier (CS)

• Most widely used
• Signal ground or an ac earth is at the source
  through a bypass capacitor
• Not to disturb dc bias current voltages
  coupling capacitors are used to pass the signal
  voltages to the input terminal of the amplifier
  or to the Load Resistance
• CS circuit is unilateral
• Rin does not depend on RL and vice versa

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Small Signal Hybrid p Model (CS)
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Small Signal Hybrid p Model (CS)
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Small-signal analysis performed directly on the
amplifier circuit with the MOSFET model
implicitly utilized.
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BJT / MOSFET
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Common Source Amplifier (CS) Summary

• Input Resistance is infinite (Ri8)
• Output Resistance RD
• Voltage Gain is substantial

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Common-source amplifier with a resistance RS in
the source lead
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The Common Source Amplifier with a Source
Resistance

• The T Model is preferred, whenever a resistance
  is connected to the source terminal.
• ro (output resistance due to Early Effect) is not
  included, as it would make the amplifier non
  unilateral effect of using ro in model would be
  studied in Chapter 6

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Small-signal equivalent circuit with ro neglected.
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Small-signal Analysis.
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Voltage Gain CS with RS
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• Source Resistance can be used to control the
  magnitude of the signal vgs thus ensure that
  vgs does not become too large to cause non-linear
  distortion
• vgs ltlt 2(VGS-Vt) ltlt 2VOV

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Common Source Configuration with Rs

• Rs causes a negative feedback thus improving the
  stability of drain current of the circuit but at
  the cost of voltage gain
• Rs reduces id by the factor
• (1gmRs) Amount of feedback
• Rs is called Source degeneration resistance as it
  reduces the gain

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Small-signal equivalent circuit directly on
Circuit
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A common-gate amplifier based on the circuit
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Common Gate (CG) Amplifier

• The input signal is applied to the source
• Output is taken from the drain
• The gate is formed as a common input output
  port.
• T Model is more Convenient
• ro is neglected

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A small-signal equivalent circuit
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A small-signal Analusis CG
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A small-signal Analusis CG
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Small signal analysis directly on circuit
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The common-gate amplifier fed with a
current-signal input.
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Summary CG

• 4. CG has much higher output Resistance
• CG is unity current Gain amplifier or a Current
  Buffer
• CG has superior High Frequency Response.

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Common Gate

• Rin in independent of RL Rin 1/gm gm in
  order of mA/V.
• Input resistance of the CG Amplifier is
  relatively low (in order of 1kv) than CS
  Amplifier
• Loss of signal
• CG is acts as Unity gain current amplifier
  current buffer useful for a Cascade circuitry

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A common-drain or source-follower amplifier.
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Small-signal equivalent-circuit model
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Small-signal Analysis CD
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(a) A common-drain or source-follower amplifier
output resistance Rout of the source follower.
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(a) A common-drain or source-follower amplifier.
Small-signal analysis performed directly on the
circuit.
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Common Source Circuit (CS)
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Common Source Circuit (CS) With RS
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Common Gate Circuit (CG) Current Follower
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Common Drain Circuit (CD) Source Follower
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Summary Comparison
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Quiz No 4
27-03-07

• Draw/Write the Following

BJT BJT MOSFET MOSFET
Types npn pnp nMOS pMOS
Symbols
p Model
T Model
gm
Re/rs
rp/rg

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Problem 5-44
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SOLUTION DC Analysis
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SOLUTION DC Analysis
IE
IB
gm 40mA/V
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Solution Small Signal Analysis
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Solution Small Signal Analysis
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Solution Small Signal Analysis Input Resistance
ib

vb
-
Rin
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Solution Small Signal Analysis Output Resistance
Itest
IE
IRC
IE/(1ß)
Rout
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Solution Small Signal Analysis Voltage Gain

veb
-
-
Vo


vi
-
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Solution Small Signal Analysis Voltage gain

veb
-

vi
-
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Solution Small Signal Analysis Voltage Gain

vi
-
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Solution Small Signal Analysis Voltage Gain
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Solution Small Signal Analysis Voltage Gain
-
Vo


vi
-
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Problem
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Small Signal Model MOSFET CD
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Solution Small Signal Analysis
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Solution Small Signal Analysis Input Resistance
Ig0
Rin
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Solution Small Signal Analysis Output Resistance
Itest
ID
IRD
0 V
Vtest
IG0
Rout
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Solution Small Signal Analysis Voltage Gain

vsg
-
-

vo
vi

-
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Solution Small Signal Analysis Voltage gain

vsg
-

vi
-
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Solution Small Signal Analysis Voltage Gain

vi
-
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Solution Small Signal Analysis Voltage Gain
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Solution Small Signal Analysis Voltage Gain
-


vi
-
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Solution Small Signal Analysis
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Transistor Pairings Amplifiers

• Common Emitter Common Base (CE-CB)
• Common Emitter Common Collector (CE-CC)
• Common Collector - Common Emitter (CC-CE)
• Common Collector - Common Base (CC-CB)

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Problem 6-127(e)
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DC Analysis 6-127(e)
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Small Signal Model
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Small Signal Model
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Small Signal Model
Rin
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Small Signal Model


vbe2
vbe1
-
-
Rout
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Small Signal Model
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Problem6-127(f)Replacing BJT with MOSFET
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Small Signal Model
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Small Signal Model
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Small Signal Model
Rin
Rout
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Problem 6-127(f)
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Solution P6-127(f)

vbe2
-

veb1
-
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Solution P6-127(f)
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Problem 6-127(f) with MOSFET
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Solution P6-127(f)

vgs2
-

vsg1
-
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Solution P6-127(f)
ig10

vi
-
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Comparison BJT/MOSFET Cct
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Problem 6-123
VBE0.7 V ß 200 Kn(W/L)2mA/V2 Vt1V
Figure P6.123
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DC Analysis
Figure P6.123
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DC Analysis
VBE0.7 V ß 200 Kn(W/L)2mA/V2 Vt11V Vt225mV
1mA
2V
0.7V
IG0
I0.7/6.80.1mA
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Small Signal Model
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Small Signal Model
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Small Signal Model Voltage Gain
ig0


vi
vbe2
-
-
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Small Signal Model Input Resistance
ii
ig0

vi
-
Rin
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Small Signal Model Output Resistance
IRG
Itest
Vtest vo
Rout
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The Miller Theorem.
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The Miller equivalent circuit.
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Miller Theorem
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Miller theorem

• Miller theorem states that impedance Z can be
  replaced by two impedances Z1 connected between
  node 1 and ground and Z2 connected between node 2
  and ground where

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Miller theorem

• Miller equivalent circuit is valid only as long
  as the rest of the circuit remains unchanged
• Miller equivalent circuit cannot be used directly
  to determine the output resistance of an
  amplifier. It is due to the fact for output
  impedance test source is required and thus
  circuit has a major change.

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Circuit for Example 6.7.
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Circuit for Example 6.7.
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Example
K-100 V/V, Z 1 M O
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OBSERVATIONS

• The Miller replacement for a negative feedback
  results in a smaller resistance by a factor of
  (1-K) at the input.
• The multiplication of a feedback impedance by a
  factor (1-k) is referred as Miller Multiplication
  or Miller Effect

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Small Signal ModelCE with RE includng r0
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A CE amplifier with emitter degeneration Input
Resistance
7
2
3
1
4
6
5
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A CE amplifier with emitter degeneration Input
Resistance
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A CE amplifier with emitter degeneration to
determine Avo.
Open Circuit Voltage Gain
Figure 6.49
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A CE amplifier with emitter degeneration to
determine Output Resistance
6
7
5
4
3
1
2
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A CE amplifier with emitter degeneration to
determine Short-Circuit Trans-conductance Gm
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Active-loaded common-base amplifier
Figure 6.33
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Active-loaded common-base amplifier to determine
Input Resistance
7
4
5
3
6
2
1
Figure 6.33
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Active-loaded common-base amplifier With output
open-circuit
6
7
5
4
3
8
2
1
Figure 6.33
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A CB amplifier to determine Output Resistance
6
7
5
4
3
1
2
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Quiz No 8 DE 28 EE
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Quiz No 8 DE 28 EE